TAGIPS, An Adaptable Parallel Processor for Imaging Applications
چکیده
The new generation 32 bit signal processing chips have architectural features that make them suitable for image processing purposes. Although the speed of a processor board with one PE does not meet the requirements of real time imaging, with some additional circuitry it is possible to construct such a board. In this paper we present a fast parallel processor for a PC bus. It uses a single 32 bit signal processing chip connected together with special convolution processors and reconfigurable logic cell arrays. INTRODUCTION The parallelization of image processing tasks has been studied extensively. A large number of special parallel architectures have been developed within the last few years. In our research of practical image processing systems the emphasis has been especially on certain design criteria: low cost of the system is obvious, both for the end-user equipment, and for the equipment used in development laboratories designing industrial applications of image processing. This requirement no longer needs to contradict with another important requirement, high speed. Recent developments in VLSI allow the design of fast but low-cost systems for a wide application range. Ideally, the same equipment and programming tools that are used in developing a system, can be used in the final product. The next criteria for an image processing system is an efficient programming environment. This requirement has traditionally been overlooked, dictated by the exotic special processor architectures used. Acommon approach is to offer a number of fixed routines and management tools for constructing the user 'program' using these routines. This approach offers a minimum amount of flexibility. We prefer more common development tools found in any low cost programming environment. To satisfy these criteria, we opted to use standard DSPcomponents with readily available development tools, and industry standard PCs as the host for the image processor with efficient user interfaces. Special processors were selected for the most computationally intensive operations found in image processing. Some important architectural features are sometimes ignored in image processing systems. Acommon approach is to have a general purpose computer connected to a fast accelerator processor. However, the high bandwidth requirement of image processing may not be met: the image frame transfer time may be a significant part of the processing time (VO overhead usually is ignored in benchmark ratings!). This problem is emphasized if slow PC expansion busses are used. Therefore our design limits image data traffic to minimum: processing is done as much in place as possible. The key feature is the capability of the processor to store images to its local memory directly from a flash A/D converter, whereafter only the interesting parts are processed. When the transfer of a full image to or from the host is required the maximum speed of the bus is achieved by the use of direct memory access logic and the full data width of the bus. Our selection for the main processing element has a maximum data bandwidth of 2*33 Mbytes/s over its two busses that can be used simultaneously. ARCHITECTURE OF TAGIPS