A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware

Synchronous Transfer Architecture (STA) is a coarse-grain reconfigurable hardware. It is modelled by using a common machine description that is suitable for both compiler and core generator. STA is a Very Long Instruction Word (VLIW) architecture and in addition it uses a non-orthogonal Instruction Set Architecture (ISA). Generating efficient code for such ISA needs highly optimizing techniques. This paper presents a basic data routing Integer Linear Programming (ILP) model for STA code generation. We will also show in this paper, the execution time of the assembly code can be dramatically reduced. The code generation can be accomplished in acceptable time and it can even be real time by reducing the degree of optimality.