In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the verification of the temporal properties of a continuous system by verifying only a finite number of its (simulated) trajectories. The proposed framework comprises two main ideas. First, we take advantage of the fact ...

A modified approach for constant delay logic style is developed in this paper to provide improved power and delay named LP-HS logic. Constant delay logic style is examined against the LP-HS logic, by analysis through simulation. It is shown that the proposed LP-HS logic has low power, delay and power delay product over the existing constant delay logic style. Multiplier accumulator unit is one ...

We describe a method for generating logic simulation code which correctly responds to any number of unde ned logic values at the code inputs. The method is based on our development of the Ordered Ternary Decision Diagram, itself based on Kleenean ternary logic, which explicitly and correctly manages the unknown logic value `U' in addition to the `1' and `0' of conventional OBDDs. We describe th...

This paper presents a simulation preorder for continuoustime Markov chains (CTMCs). The simulation preorder is a conservative extension of a weak variant of probabilistic simulation on fully probabilistic systems, i.e., discrete-time Markov chains. The main result of the paper is that the simulation preorder preserves safety and liveness properties expressed in continuous stochastic logic (CSL)...

This paper deals with delay fault simulation of logic circuits in the context of IR-drop induced delay. An original algorithm is proposed allowing to perform a per-cycle delay simulation of the logic Block Under Test (BUT) while taking into account the whole chip IR-drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN)...

Logic-level simulation is still one of the most often used operations on digital designs during both design and test stages. This makes it a critical issue affecting the overall cost of a project. In this paper we investigate and show the origins of common advantages of four recently proposed efficient simulation methods of different classes: logic simulation, multi-valued simulation, timing si...

We illustrate TeQsim, a qualitative simulator for continuous dynamical systems that combines the expressive power of qualitative diierential equations with temporal logic to constrain and reene the resulting predicted behaviors. Temporal logic is used to specify constraints that restrict the simulation to a region of the state space and to specify trajectories for input variables. A proposition...

We illustrate TeQsim, a qualitative simulator for continuous dynamical systems that combines the expressive power of qualitative diierential equations with temporal logic to constrain and reene the resulting predicted behaviors. Temporal logic is used to specify constraints that restrict the simulation to a region of the state space and to specify trajectories for input variables. A proposition...

This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions due to nite propagation delays, it is ...