In this paper, underlap channel dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been proposed, in which the increased effective channel length (Leff) due to underlap channel at both source/drain (S/D) sides reduces the leakage currents, short-channel effects and the parasitic capacitances as compared to overlap channel DSSB SOI MOSFET. Although in strong inversion the voltage drop acro...

The deep roots and wide branches of the K(+)-channel family are evident from genome surveys and laboratory experimentation. K(+)-channel genes are widespread and found in nearly all the free-living bacteria, archaea and eukarya. The conservation of basic structures and mechanisms such as the K(+) filter, the gate, and some of the gate's regulatory domains have allowed general insights on animal...

The experimental characterization of gate capacitance in nanoscale devices is challenging. We report an application of the charge-based capacitance measurement (CBCM) technique to measure the gate capacitance of a single-channel nanowire transistor. The measurement results are validated by 3-D electrostatic computations for parasitic estimation and 2-D self-consistent sp3s∗d tight-binding compu...

Partial-Response Maximum-Likelihood (PRML) coding techniques overcome problems associated with intersymbol interference (ISI) on the premise that, once this interference is known, its effect can be removed. A core part of the analogue front-end of a PRML read channel, and the subject of this paper, is a continuous-time low-pass filter which carries out both pulse-shaping and noise-filtering. Th...

using of nanofluids and ducts with corrugated walls are both supposed to enhance heat transfer, by increasing the heat transfer fluid conductivity and the heat transfer area respectively. use of a diverging duct with a jet at inlet section may further increase heat transfer by creating recirculation zones inside the duct. in this work two-dimensional incompressible laminar flow of a nanofluid e...

Simulation results on a novel extended p dual source SOI MOSFET are reported. It is shown that the presence of the extended p region on the source side, which can be fabricated using the post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the l...

Delay analysis providing an alternative physical explanation on carrier transport, which may be more applicable to high electron mobility transistor (HEMT) channels with moderate carrier mobilities, has been applied to enhancement-mode (E-mode) and depletion-mode (D-mode) InAlN/AlN/GaN HEMTs with comparable fT at room and cryogenic temperatures. It was found that the speed of the E-mode HEMTs w...

In this paper an attention is paid to the existence of parasitic elements in a typical n-channel MOSFET devices that are often employed in sub-THz detectors and the role they play in when such devices are employed at sub-THz frequencies. An effective circuit model of such a structure was constructed. The most of the effort was put to investigate the influence of the layout of the MOSFET’s Gate ...

Solution-based organic field-effect transistors (OFETs) with low parasitic capacitance have been fabricated using a self-aligned method. The self-aligned processes using a cross-linking polymer gate insulator allow fabricating electrically stable polymer OFETs with small overlap area between the source-drain electrodes and the gate electrode, whose frequency characteristics have been investigat...

There is strong demand to maintain the trend of increasing bit density and reducing bit cost in Flash memory technology. To this end, aggressive scaling of the device dimension and multi-level cell (MLC) or multi-bit cell (MBC) have been proposed in NAND and NOR Flash memory architectures. However, especially in NAND Flash memory, bit cost is expected to rise in the near future, because the pro...