in biaxially strained p-mosfet with si channel, formation of a parasitic parallel channel due to misalignment of energy bands degrades device performance by increasing off-state current. in this paper a new approach has been introduced to eliminate this parasitic channel by increasing the dopant concentration of virtual substrate up to . using simulation the impact of this method on the parasit...

this paper proposes a new smart antenna beamforming scheme based on electronically steerable parasitic array radiator (espar). the proposed method is capable of providing better capacity compared to the conventional espar. the termination of each antenna element in this structure comprises a pin diode in addition to a varactor. using pin diode besides the varactor provides more degrees of freed...

This paper proposes a channel capacity maximization method for Multiple-Input Multiple-Output (MIMO) antennas with parasitic elements. Reactive terminations are connected to the parasitic elements, and the reactance values are determined to achieve stochastically high channel capacity for the environment targeted. This method treats the S-parameter and propagation channel of the antenna, includ...

Wenyao XU Fengbo REN Background on process variation and Leakage With technology scaling, the MOS device channel length is reduced. As the channel length approaches the source-body and drain-body depletion widths, the charge in the channel due to these parasitic diodes become comparable to the depletion charge due to the MOS gate-body voltage [Poon et al. 1973], rendering the gate and body term...

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities ( gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is obs...

A two-dimensional analysis of punch-through effects in high voltage lateral DMOS transistors is presented. The behaviour of these devices has been investigated for various doping concentrations. For one doping profile punch-through occurs between 6V and 60V drain voltage depending on the gate voltage, for the other doping profile no parasitic channel is built up even at lOOV drain voltage. Furt...

In vertebrates, connexins (Cxs) and pannexins (Panxs) are proteins that form gap junction channels and/or hemichannels located at cell-cell interfaces and cell surface, respectively. Similar channel types are formed by innexins in invertebrate cells. These channels serve as pathways for cellular communication that coordinate diverse physiologic processes. However, it is known that many acquired...

Device miniaturization is an important part of VLSI design, which refers to reduction in dimension of device by keeping all other characteristic constant. As technology node is moving in submicron region, the performance of the device degrades due to short channel effects and narrow channel effects. The key issues due to these effects are draininduced-barrier– lowering (DIBL), leakage current, ...