Today power consumption is considered to be one of the important issues. Therefore, its reduction plays a considerable role in developing systems. Previous studies have shown that approximately 50% of total power consumption is used in cache memories. There is a direct relationship between power consumption and replacement quantity made in cache. The less the number of replacements is, the less...

quantum-dot cellular automaton (qca) is a novel nanotechnology with a very different computational method in compared with cmos, whereas placement of electrons in cells indicates digital information. this nanotechnology with specifications such as fast speed, high parallel processing, small area, low power consumption and higher switching frequency becomes a promising candidate for cmos technol...

Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. We propose a novel leakage reduction technique, named “sleepy stack,” which can be applied to general logic design. Our sleepy stack approach retains exact logic state – making it...

SRAM is designed to provide an interface with CPU and to replace DRAMs in systems that require very low power consumption. Low power SRAM design is crucial since it takes a large fraction of total power and die area in high performance processors. A SRAM cell must meet the requirements for the operation in submicron/nano ranges. 8T SRAM is traditionally concerned as a more reliable memory cell,...

In the past, the major concerns of the VLSI designer were area, performance, and cost; power consumption considerations were mostly of secondary concern. In recent years, however, this trend has begun to change, and, increasingly, power consumption is being given comparable weight to area and speed in VLSI design (Rabaey and Pedram 1996). One reason is that the continuing increase in chip scale...

Body Area Networks (BANs) has great potential to provide real-time health monitoring of a patient and diagnose many life threatening diseases. The wireless capsule endoscopy (WCE) is one of the promising wireless Body Area Networks (WBANs) applications that provides a noninvasive way to inspect the entire Gastrointestinal (GI) tract. The low operating power of the capsule is the most critical f...

This paper introduces an efficient application intended for mapping under complex criteria applied to K-LUT based FPGA implemented circuits. This application is based on an algorithm that was developed taking into consideration a significant design factor power consumption. Power consumption is considered in addition to other design factors that are traditionally used. To increase performance, ...

This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. The design was simulated with Modelsim, and synthesized with Synopsys in three CMOS technologies with different gate lengths: 180nm, 130nm and 90 nm. The aim of this paper is to evaluate the suitability of this technique and compare the power consumption and ...

The paper presents a new logic optimization method of multi-level combinational CMOS circuits, which minimizes area and power. Present methods to reduce power on logic circuits apply functional methods like logic factorization on the Boolean networks. The method described here uses Boolean transformations that exploit implications at the gate-level based on both controllability and observabil-i...