The design of A 2.4-GHz CMOS Class E cascode power amplifier (PA) for GSM applications in TSMC 0.18-μm CMOS technology present in this paper. Proposed Class E cascode PA topology is a single-stage topology in order to minimize the device stress problem. A parallel capacitor is connected across the transistors for efficiency enrichment also for dominating the effect of parasitic capacitances at ...

This paper presents a balanced receiver structure suitable for wireless infrared data communications. The receiver provides a fixed photodiode bias voltage with the use of a regulated cascode input stage. Together with an active feedback loop used to eliminate dc photocurrents, the receiver implements ac coupling without the need for matching capacitors. Differential sensing of the photodiode c...

This work proposed a low power and high gain folded cascode CMOS operational amplifier with a common mode feedback (CMFB) for Pipeline ADC. The proposed design is implemented in 0.13-μm Silterra CMOS technology. The folded cascode topology has been used for obtaining a high gain and low power consumption. Meanwhile, the CMFB is modified circuit to be a double detection to stabilize the output o...

A gain boosting method without noise-figure degradation by optimizing interstage matching in a cascode low-noise amplifier (LNA) with emitter-degeneration inductor is demonstrated at 5.2 GHz using 2m GaInP/GaAs HBT technology. A low-pass LC matching network is inserted in the interstage of a conventional cascode LNA with emitter-degeneration-inductor to enhance the gain with the same current co...

Low Noise Amplifier and Mixer design considerations for 2.45 GHz Bluetooth applications have been studied. A detailed noise analysis is presented. A design strategy for an inductively degenerated common-source LNA with cascode transistor and current-commutating Mixer is proposed, considering the tradeoffs between noise, linearity, power consumption and matching of impedances. Additionally, this...

This paper addresses the issues involved in designing 1V Op-amp in standard digital CMOS technology. Bulk-driving technique is used to circumvent the metal–oxide semiconductor field-effect transistor turn-on (threshold) voltage requirement. The Op-amp will be designed in a Europractice 0.7μm n-well CMOS process having threshold voltage of 0.76V and –1V for NMOS and PMOS respectively. Simple and...

A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous...

Now a day’s technology enhancement is at a blistering pace. Merely VLSI has a meteoric rise due to the adoption of new techniques. Static CMOS had a limitation of deploying constant power supply. Less power dissipation is an essential attribute for any optimized design. Varying the power supply is the very thing for preventing the power dissipation. An adiabatic logic is a new technique to redu...