This paper proposes a novel, tunable AC coupled capacitive feedback amplifier, exhibiting an ultra-low high pass corner frequency. is accomplished by actively boosting the output resistive value of MOS transistor in weak inversion. The circuit based on more general architecture, recently proposed authors, and analyzed terms its capability to achieve frequency operation, DC performance, noise. t...

In this paper we proposed a three stage pipelined finite-impulse response (FIR) filter, this FIR filter contains multipliers such as Hybrid multiplier, Booth multiplier algorithm and Array multiplier. In general, multiplication process consists of two parts as multiplicand and multiplier. According to the array multiplier, the numbers of partial products (PP) are equal to the number of bits in ...

In this paper, we present a novel and efficient method for the design of a sharp, two dimensional (2D) wideband, circularly symmetric, FIR filter. First of all, a sharp one dimensional (1D) infinite precision FIR filter is designed using the Frequency Response Masking (FRM) technique. This filter is converted into a multiplier-less filter by representing it in the Canonic Signed Digit (CSD) spa...

This paper presents a novel discrete particle swarm optimization (PSO) for frequency response masking (FRM) finite impulse response (FIR) digital filters over the canonical signed-digit (CSD) multiplier coefficient space. A look-up table (LUT) scheme is employed to ensure that the PSO automatically searches through permissible CSD multiplier coefficient values in the course of optimization with...

— It is well known that frequency response masking (FRM) FIR digital filters can be designed to exhibit very sharp-transition bands at the cost of slightly larger filter lengths as compared to the conventional FIR digital filters. The FRM FIR digital filters permit efficient hardware implementations due to an inherently large number of zero-valued multiplier coefficients in their transfer funct...

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8m N-well doublepoly-double-metal CMOS technology. Experimental ...

Multipliers of reproducing kernel Hilbert spaces can be characterized in terms positivity $n \times n$ matrices analogous to the classical Pick matrix. We study for which it suffices consider bounded size $n$. connect this problem notion subhomogeneity non-selfadjoint operator algebras. Our main results show that multiplier algebras many analytic functions, such as Dirichlet space and Drury-Arv...

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed.  This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...