An intermediate frequency (IF) variable gain amplifier (VGA) with exponential gain control for a radio receiver is fabricated in 0.25-μm CMOS technology. The techniques to improve the bandwidth and to reduce temperature dependence of gain are described. The complete VGA is composed of two stages of linearized transconductance VGA and three stages of fixed gain amplifier (FGA). The complete VGA ...

This paper presents a design of 2.4 GHz low noise amplifier (LNA) for wireless sensor network (WSN) applications using CMOS 0.13 μm Silterra process. The proposed LNA employs a self-biased inverter to obtain high gain and able to operate at low supply voltage. The simulation results indicated that the proposed LNA achieves an input return loss (S11) of -37.7 dB, output return loss (S22) of -28....

This report describes a sub-harmonic mixer for WCDMA applications. The circuit converts a 2 GHz RF signal directly to baseband using a 1 GHz LO frequency. The mixer uses common source MOSFETs with inductive degeneration to convert the input RF voltage to a current. This current is then steered using a switching network composed of triode-region MOSFETs that is driven with the LO and a 90 degree...

This paper presents an ultra-wideband (UWB) low noise amplifier (LNA) using two stage cascading topology to obtain high gain. Inductive degeneration and peaking inductor techniques are used to obtain wideband matching and flatness of gain. The proposed UWB LNA is implemented by using 180nm based CMOS TSMC technology using Advanced Design System (ADS) software.LNA achieves maximum gain of 15.5dB...

This paper presents a Sub-mW differential Common-Gate Low Noise Amplifier (CGLNA) for ZigBee standard. The circuit takes the advantage of shunt feedback and Dual Capacitive Cross Coupling (DCCC) to reduce power consumption and the bandwidth extension capacitors to support 2.4 GHz ISM band. An amplifier employing these techniques has been designed and simulated in 0.18 mm TSMC CMOS technology. T...

An ultra-wideband low noise amplifier for cognitive radio applications covering 50 MHz to 10 GHz is designed in a 65-nm CMOS technology. A three-stage dc-coupled common source amplifier with RC degeneration at the last stage optimizes the gain, linearity and output gain-phase balancing. Throughout the covered band, the simulated voltage gain is >23.3 dB whereas the noise figure is <3.4 dB. The ...

In this paper, a CMOS low power amplifier based on a high-quality active inductor and implemented by using 0.25-μm 1P5M CMOS standard technology is presented. The amplifier achieves power gain (S21) of 18dB within the -3dB cutoff frequency, bandwidth of 1.3GHz, and power consumption of 18mW under 2.5V power supply in 188 × 174μm silicon area. The input third-order intercept point (IIP3) and the...

This paper discusses the design, analysis and performance of a 2.4 GHz fully integrated low-power current-reused receiver front-end implemented in 0.18 μm CMOS technology. The front-end is composed of a single-to-differential low-noise amplifier (LNA), using high-Q differential transformers and inductors and a coupled switching mixer stage. The mixer transconductor and LNA share the same DC cur...

A new low power 33 GHz low noise amplifier (LNA) is proposed in a 0.18μm CMOS technology. It is composed of a single-stage cascode topology consisting of two Common-Gate (CG) amplifiers which provides gain requirements in high frequencies with very low power dissipation. The designed LNA achieves a power gain of 12 dB, IIP3 of -1dBm, and noise figure from 2.96-3.86 dB over the 3dB bandwidth fro...