We have investigated a chaotic circuit utilizing CMOS ring oscillators[1]. The circuit consists of two CMOS ring oscillators and two diodes. A CMOS ring oscillator is used for CMOS process performance test. This oscillator consists of a series of inverter circuits. It has a very simple structure. Therefore, we consider that the proposed circuit is realized very easily. In the past studies, we h...

Due to substantial mixed analog-digital circuit integration in one chips CMOS digital imager cannot be considered only as a photoelectric transducer. In this paper, we have identzjied timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip. An optimized binaryscaled tree-topology power routing has been shown to be critical for minimizing chip ...

This paper presents JPL progress in building evolutionoriented reconfigurable devices. It surveys the FPTA family, and presents details of the latest chip, FPTA2, an array of 64 reconfigurable cells that can implement mixed-signal functions, include programmable capacitors and resistors and integrate photodetectors as part of a built-in vision sensor. The chip was fabricated in 0.18 micron CMOS...

Many single-electron devices and circuits that realize CMOS-like digital logic were proposed so far (Takahashi, Ono, Fujiwara, & Inokawa, 2002). However, the single-electron circuit technology should aim at developing computing systems that perform information processing by using singleelectron phenomena (Morie, & Amemiya, 2006). Because their operation principles are completely different from ...

In this paper, the importance and perspective for the digitally-assisted analog and RF circuits are discussed, especially related to wireless transceivers. Digital calibration techniques for compensating I/Q mismatch, IM2, and LO impairments in cellular, 2.4GHz WiFi, and 60GHz WiGig transceivers are introduced with detailed analysis and circuit implementations. Future technology directions such...

Optical transimpedance receivers implemented in CMOS VLSI technologies are modeled and optimized for freespace optoelectronic interconnections. Sensitivity, bandwidth, power dissipation, and circuit area are analyzed for receivers using three different submicron CMOS processes. A comparison with the circuit noise limited optical power indicates that, for digital computing applications, the rece...

Table 1 Classical constant-field scaling rules and consequences. 1. CLASSICAL CMOS SCALING Voltages Vth, VDS 1/α Dimensions Lateral and vertical 1/α Electric field V/L, V/d const. Conductance I/V const. Capacitance 1/α Speed I/CV α Switching energy CV 1/α Power/gate CVf 1/α Transistor density 1/L α Power density const. The essential aspects of CMOS digital circuit behavior can be understood by ...

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a ...