Adders and multipliers are two main units of the computer arithmetic processors and play an important role in reversible computations. The binary multiplier consists of two main parts, the partial products generation circuit (PPGC) and the reversible parallel adders (RPA). This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced PPGC with Peres gates only. Ag...

We prove L estimates (Theorem 1.2) for the “biest”, a trilinear multiplier operator with singular symbol. The methods used are based on the treatment of the Walsh analogue of the biest in the prequel [16] of this paper, but with additional technicalities due to the fact that in the Fourier model one cannot obtain perfect localization in both space and frequency.

This paper is devoted for designing high speed arithmetic logic unit. All of us know that ALU is a module which can perform arithmetic and logic operations. The reason behind choosing this topic as a research work is that, ALU is the key element of digital processors like as microprocessors, microcontrollers, central processing unit etc. Every digital domain based technology depends upon the op...

A low power, adaptive bandwidth tracking Phase Locked Loop (PLL) is presented in this paper. Designed PLL operates over a wide frequency range of 250MHz to 1GHz with a fixed multiplication factor of 8. PLL is optimized for 0.2% UI of r.m.s. jitter over the whole frequency range with bandwidth tracking to keep the power consumption minimum. In addition, a multiplier block is used to increase the...

We present a programmable continuous-time floating-gate Fourier processor that decomposes the incoming signal into frequency bands by analog bandpass filters, multiplies each channel by a nonvolitile weight, and then recombines the frequency channels. A digital signal processor would take a similar approach of computing a fast Fourier transform (FFT), multiplying the frequency components by a w...

A 4x4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4x4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus...

A 4x4 and 8x8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4x4 and 8x8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multipli...

In this work, a non-isolated high step up DC-DC converter using coupled inductor and voltage multiplier cell is proposed. The proposed converter conversion ratio is efficiently extended by using a coupled inductor. An interleaved configuration of two diode-capacitor cells is applied to step up the voltage conversion ratio and decrease the voltage stress across the switches. Also, in the suggest...

List of Symbols 12.1 Concepts, Definitions, and Measures of Stabilitv 12.1 .l Relationship between the Power Spectrum and the Phase Spectrum 12.1.2 The IEEE Recommended Measures of Frequency Stability 12.1.3 The Concepts of the Frequency Domain and the Time Domain 12.1.4 Translation between the Spectral Density of Frequency and the Allan Variance 12.15 The Modified Allan Variance 12.1.6 Determi...

In this letter, the ambipolar transport properties of graphene flakes have been used to fabricate full-wave signal rectifiers and frequency-doubling devices. By correctly biasing an ambipolar graphene field-effect transistor in common-source configuration, a sinusoidal voltage applied to the transistor gate is rectified at the drain electrode. Using this concept, frequency multiplication of a 1...