This work proposes a quasi-passive reconfigurable complex filter with harmonic rejection based on N-path filtering technique. It features extremely low power consumption and center frequencies. Unlike the traditional filters at RF frequencies, proposed achieves 3rd/5th adjacent frequencies by cascading different clock The is implemented in 55nm CMOS technology, consumes an area of 0.24mm2 inclu...

Applications In this paper A single chip 2.4GHz low power CMOS receiver and transmitter for WPAN applications are implemented and measured. The receiver uses a low-IF architecture with a polyphone filter and transistor linearization technique to improve linearity per power, and the transmitter adopts a ROM based direct-conversion architecture for low power consumption and high integrated densit...

This paper reports a comprehensive design methodology and compact multilayer integration concept for fully-reconfigurable bandpass filtering (BPF) manifold with simultaneous ultrawide center frequency bandwidth (BW) tuning. The is based on two RF-switched tune-all BPFs whose transfer function shaped by three-poles transmission zeros (TZs) (i.e., three-pole/two-TZs). Tunability can be achieved s...

This article presents an agile passive-mixer-first superheterodyne RF front-end that utilizes a gigahertz acoustic filter as its intermediate-frequency (IF) load-essentially mixer-first acoustic-filtering front-end. The passive mixer frequency-translates sharp but fixed-frequency response to much higher and mixer-clock-defined tunable frequency while preserves input matching, high linearity, in...

The pHEMT heterostructures optimized in this work to improve the parameters of switching microwave transistors have a one-sided δ-doping at 6×1012 cm-2 and an AlAs/GaAs spacer. Such were used fabricate monolithic integrated circuits single-pole double throw switches with gate length width 0.5 μm 100 μm, respectively. resulting had following parameters: gm = 400 mS/mm, saturation current ID=380 ...

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for ...