Sequencing problems have to be solved very often in VLSI CAD. To obtain results of high quality, Evolutionary Algorithms (EAs) have been successfully applied in many cases. However, they often suuer from the high CPU time which is necessary for the computation. In this paper we propose three techniques to speed up EAs without loss of quality. We give a case study for the problem of optimizing t...

The advent of VLSI technology and the increasing complexity of digital systems has led to the development of sophisticated CAD tools that use Hardware Description Languages (HDLs) to describe hardware designs at various levels. Based on the recent industry shifts, it has become clear that HDLs are rapidly becoming an integral part of design automation environments. This will create a demand for...

This report describes work performed on the Restructurable VLSI Program sponsored by the Information Processing Techniques Office of the Defense Advanced Research Projects Agency during the period 1 October 1984 through 31 March 1985.

A previous hierarchical fault tracing method for combinational circuits which requires only CAD layout data in the CAD-linked electron beam test system is expanded as applicable to sequential circuits. The characteristics in the method remains unchanged that allows us to trace a fault hierarchically from the top level cell to the lowest primitive cell and from the primitive cell to the transist...

Presents information on the 2022 VLSI Symposium.

Perhaps the most significant trend in the automated test equipment industry is the move toward fully integrating ATE into the CAD environment. ATE has traditionally been isolated from CAD; this gap is a serious one in terms of turnaround in VLSI device development and production. It is particularly serious in the context of semicustom VLSI chips, where an application-specific IC must be produce...

tion (VLSI), to domains other than mere logic devices. The feasibility of building small sensory devices, actuators, and motors was demonstrated by a number of microelectromechanical systems (MEMS) researchers. MEMS technology is not associated with one particular process, but rather encompasses a rich variety of process flows. Devices are fabricated by a sequence of conventional VLSI unit proc...

In this paper, models of input admittance of RC interconnects are discussed in depth to understand and evaluate their loading effects on driving CMOS gates. From a detailed analysis of input admittance polezero location, arguments are derived to prove that their input admittance can be accurately approximated to that of a low-order equivalent RC circuit, in contrast to the case of timing analys...

Project focus: The MADE program focuses on problems of design and manufacture of complex electro-mechanical (CEM) items like seeker heads and disk drives, an area that does not have a single technical focus or well developed engineering models. Practitioners deal in many technologies, including nontechnical ones like organizations and corporate cultures, and make heavy use of their experience t...