The mammalian circadian clock is a critical regulator of metabolism and cell division. Although multiple lines of evidence indicate that systemic disruption of the circadian clock can promote cancer, whether the clock is disrupted in primary human tumors is unknown. Here we used transcriptome data from mice to define a signature of the mammalian circadian clock based on the co-expression of 12 ...

Matrix clock is a generalisation of the notion of vector clock. Matrix clock is a mechanism for capturing chronological and causal relationship in a Distributed system. Matrix clock is a list of vector clocks, and it also contains the current state of each node in the system. On the basis of this it know which peer received already which messages. When it exchanges messages with another node in...

Circadian rhythm disruptions are prominently associated with bipolar disorder (BD). Circadian rhythms are regulated by the molecular clock, a family of proteins that function together in a transcriptional-translational feedback loop. The CLOCK protein is a key transcription factor of this feedback loop, and previous studies have found that manipulations of the Clock gene are sufficient to produ...

Process-variation induced skew has become one of the major contributors to the clock-skew in advanced technologies. Since process-variation induced skew is roughly proportional to clock-delay, it is preferable to design zero-skew clock-trees and have minimum clock-delay to reduce both unintentional and process-variation induced skews. In this paper, we propose a zero-skew buffered clock-tree sy...

A further research on floorplanning considering multi clock domains is presented in this paper, which concentrates on interconnection between different clock domains. This contributes to simplification of clock tree and signal routing between different clock domains. Experimental results show that better floorplan can be obtained through our floorplanning proposed in this paper. Key-Words: Floo...

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock-gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip flops to generate a derived clock for each flip flop in the circuit. A technique for clock gating is also ...