This is a VLSI implementation of a VGA Controller. It uses a custom cell library developed in Cadence for a half micron process. The VGA controller is designed in verilog. It is a coprocessor for an external CPU.

This paper presents a low-power, 32-bit RISC microprocessor with a 64-bit “single-instruction multiple-data” multimedia coprocessor, V830R/AV, and its MPEG-2 video decoding performance. This coprocessor basically performs multimedia-oriented four 16-bit operations every clock, such as multiply-accumulate with symmetric rounding and saturation, and accelerates computationally intensive procedure...

Sub-block oriented media processor architecture is presented. A block oriented instruction set extension is proposed to process and transfer 1D or 2D data blocks. Two programmable processors are employed to perform sequential processing and block oriented processing respectively. We evaluated the performance potential of the media processor architecture using a special FPGA card, and an image F...

Elliptic curve cryptography (ECC) provides high security with shorter keys than other public-key cryptosystems and it has been successfully used in security critical embedded systems. We present an FPGA-based coprocessor that communicates with the host processor via a 32-bit bus. It implements ECC over an elliptic curve that offers roughly 128-bit security. It is the first hardware implementati...

Nowadays, the use of digital communication systems has increased in such a way that network bandwidth is affected. This problem can be solved by implementing data compression algorithms in communication devices to reduce the amount of data to be transmitted. However, the design of large hardware data compression models implies to consider an efficient use of the silicon area. This work proposes...

Embedded systems present a tremendous opportunity to customize the designs by exploiting the application behavior. Shrinking time-to-market, coupled with short product lifetimes create a critical need for rapidly explore and evaluate candidate System-on-Chip(SOC) architectures. Recent work on language driven Design Space Exploration (DSE) uses Architecture Description Language (ADL) to capture ...

Eclipse defines a heterogeneous multiprocessor architecture template for data-dependent stream processing. Intended as a scalable and flexible subsystem of forthcoming media-processing systems-on-a-chip, Eclipse combines application configuration flexibility with the efficiency of function-specific hardware, or ‘coprocessors’. The multi-tasking coprocessors concurrently execute application task...

In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector coprocessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerat...

Recently Graphics Processing Units (GPUs) have been used to speed up very CPU-intensive gravitational microlensing simulations. In this work, we use the Xeon Phi coprocessor to accelerate such simulations and compare its performance on a microlensing code with that of NVIDIA’s GPUs. For the selected set of parameters evaluated in our experiment, we find that the speedup by Intel’s Knights Corne...