This paper proposes a 32-bit RISC-V microprocessor for the IoT, which consists of Hummingbird e203 and configurable precision COordinate Rotation Digital Computer (CORDIC) coprocessor. Coprocessor is used to enhance processing power system. Custom instructions are added original instruction set accelerate complex calculations. Experimental results demonstrate that coprocessor can process applic...

This paper deals with the design of a mathematical coprocessor using RISC based approach. The coprocessor can relieve the main processor of large matrix based computations usually used in the field of image processing, cryptography, etc. The protocol for communication of the processor with the computer is also designed in the project. The timing required for the designed processor is checked wi...

Recently, computer architectures that combine a reconng-urable (or retargetable) coprocessor with a general-purpose microprocessor have been proposed. These architectures are designed to exploit large amounts of ne grain par-allelism in applications. In this paper, we study the performance of the reconngurable coprocessors on multimedia applications. We compare a Field Programmable Gate Array (...

Recently, computer architectures that combine a recon gurable (or retargetable) coprocessor with a general-purpose microprocessor have been proposed. These architectures are designed to exploit large amounts of ne grain parallelism in applications. In this paper, we study the performance of the recon gurable coprocessors on multimedia applications. We compare a Field Programmable Gate Array (FP...

A hardware coprocessor for the rapid calculation of bioinformatic sequence alignments is presented. The coprocessor uses a globally-asynchronous locally-synchronous (GALS) design style which makes the coprocessor much easier to scale as CMOS feature sizes decrease. The coprocessor is intended to be implemented on a single integrated circuit along with a simple 32-bit RISC processor and memory s...

In this study, a scalable coprocessor for accelerating the Differential Evolution (DE) algorithm is presented. The coprocessor is interfaced with PowerPC embedded processor of Xilinx Virtex-5 FX70T Field Programmable Gate Array. In the proposed design, the DE algorithm module is tightly coupled with fitness function module to reduce communication and control overhead. The fixed point DE algorit...

In this report we investigate the benefits of using a coprocessor coupled with content addrassible memory (CAM) for off-loading of a computation-intensive kernels of antivirus software. Overview of antivirus technologies is presented, followed by performance analysis of real antivirus software to justify the application of coprocessor. High level architecture of the coprocessor and its interact...

In this paper we present a scheduling coprocessor device for uniprocessor computer systems running a real-time operating system (RTOS). The coprocessor shortens the scheduling time of the operating system by performing dynamic priority computation for all tasks in parallel and making a task selection according to these priorities at a higher speed than a software solution would do. This paper s...