In the analysis of extra-vascular plasma concentration-time profiles, the disentanglement of influences from disposition and absorption rate influences is often challenging. This can be particularly true when absorption is considerably slower than disposition, that is, in a “flip-flop” system. The purpose of this communication is to define a pharmacokinetic flip-flop system (in a linear system)...

Experimental investigations have been conducted to improve the cooling effectiveness of film-cooling technology. A multiple row cylindrical holes at flat surface was considered by inclining 35° along streamwise direction. low-speed wind tunnel with main flow speed 10 m/s devised create a cross Reynolds number 196,167 and five blowing ratios 0.3, 0.5, 0.7, 1, 2. The proposed triangular-shaped th...

1941 1 (Floating Point operations / second, Flop/s) 1945 10

Submitted: Jan 13, 2013; Accepted: Feb 26, 2013; Published: Aug 18, 2013 Abstract: This paper presents the design and performance evaluation of a modified complementary energy path adiabatic logic (MCEPAL) circuit. A simulative investigation on the proposed MCEPAL based, multiplexer, JK flip flop and 3 bit counter has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technolog...

The clock distribution network in digital integrated circuits distributes the clock signal which acts as a timing reference controlling data flow within the system. Since the clock signal has highest capacitance and operates at high frequencies, the clock distribution network consumes a large amount of total power in synchronous system. So, a new flip-flop is proposed in a low-swing resonant cl...

In this paper, we propose a new architecture of non-volatile Flip-Flop based on ReRAM unipolar resistive memory element (RNVFF). This architecture is proposed in the context of power-down applications. Flip-Flop content is saved into ReRAM memory cell before power-down and restored after power-up. To simulate such a structure a compact model of unipolar ReRAM was developed and calibrated on bes...

In this paper, a low power implicit type pulsed flip-flop (PFF) using self-driven pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. The pass transistor logic driven by generated clock pulse is used directly to drive the output of the flip-flop. The proposed de...

The AMPA-type glutamate receptor (AMPAR) subunit composition shapes synaptic transmission and varies throughout development and in response to different input patterns. Here, we show that chronic activity deprivation gives rise to synaptic AMPAR responses with enhanced fidelity. Extrasynaptic AMPARs exhibited changes in kinetics and pharmacology associated with splicing of the alternative flip/...

Practically, clocking system like flip-flop (FF) consumes large portion of total chip power. In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. Pulsetriggered FF (P-FF) has been considered as a popular alternative to the conventional master –slave based FF in the applications of high speed. First, a simple two-transistor AND gate design is used to reduce the ci...

In this paper, we introduce design models for Totally Self Checking, Code Disjoint (T S C / C D) and Strongly Fault Secure, Strongly Code Disjoint (SFS/SCDJ synchronous controllers. The T S C / C D and SF / S C D models based on two new proposed low-cost, modular, Totally Self Checking (TSC), edge triggered and error propagating (code disjoint) Flip-Flops; one, a D Flip-Flop which can be used i...