The proposed two types of multi-valued D flip-flops are NMAX-TG D flip-flop and NMIN-TG D flip-flop A NMAX-TG D flip-flop and a NMIN D flip-flop are composed of the components such as NMAX D flip-flops, NMIN D flip-flops and T-gate circuits. In the simulations, sampling frequencies of NMAX-TG D flip-flop and NMIN-TG D flip-flop are measured around 500 kHz and 1 MHz, respectively. The PDP parame...

In this paper, based on the coupled-mode and carrier rate equations, a dynamic model and numerical analysis of a multi quantum well (MQW) chirped distributed feedback semiconductor optical amplifier (DFB-SOA)  all-optical flip-flop is precisely derived. We have analyzed the effects of strains of QW and MQW and cross phase modulation (XPM) on the dynamic response, and rise and fall times of the ...

Timing Optimization is one of the most important objectives of the designer in the Modern VLSI world. Memory elements play a vital role in Digital World. The basic memory elements of designer considerations are Latch and flip flop. In this paper, we analyze the design of Single-bit Flip flop (SBFF) and made performance comparison over the Multi-bit Flip-flop (MBFF). For improving Flip flop perf...

The paper presents the concept of existing D fuzzy flip-flop design and analyses the working of the design. The existing design has been studied for its delay parameters and variability. Comparisons with the previous designs has been done to lay down the superiority of the fuzzy design over existing binary flip-flop designs. Keywords— Binary flip-flop, Fuzzy flip-flop, D fuzzy flip-flop, delay,...

The timing elements and clock interconnection Networks such as flip-flops and latches, is One of the most power consuming components in modern very large Scale integration (VLSI) system. The area, power and transistor count will compared and designed using several latches and flip flop stages. Flip Flop is a circuit which is used to store state information. Power consumption is one of the main ...

The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other exis...

This paper enumerates a low power, high speed design of flip-flop having less number of transistors. In flip-flop design only one transistor is being clocked by short pulse train which is known as True Single Phase Clocking (TSPC) flip-flop. The true single-phase clock (TSPC) is common dynamic flip-flop which performs the flip-flop operation with little power and at high speeds. In this paper, ...

The authors introduce two low-cost, modular, totally self checking (TSC), edge triggered and error propagating (code disjoint) flip-flops: one, a D flip-flop used in TSC and strongly fault secure (SFS) synchronous circuits with two-rail codes, the other a T flip-flop, used in a similar way as the D flip-flop but retaining the error as an indicator until the next presetting, to aid error propaga...

Most digital systems textbooks treat the topic of converting one flip flop to another by simply giving the student certain simple conversion circuits, such as the use of an inverter between the R and S inputs of an RS flip flop to form a D flip flop, or tying together the inputs of a JK flip flop to make a T flip flop. However, a more general, but very simple, methodology for flip flop conversi...