This paper presents a new processing cell circuit, suitable for use in massively parallel fine-grain processor arrays, oriented towards image processing applications. The design, based on dynamic logic, is efficient for both local and global operations. In this paper we discuss design trade-offs and provide detailed description of the architecture. A cellular processor array based on the presen...

We show that the satisfiability problem for quantifier-free theory of product structures with equicardinality relation is in NP. As an application, we extend combinatory array logic fragment to handle cardinality constraints. The resulting independent base element and index set theories.

In this communication we propose a scheme for implementing a fuzzy processor on pro grammable logic circuits FPGA utilizing pipelined structures We have partitioned the processor structure in several sections which correspond to di erent integrated cir cuits Such I C carry out the operations in herents in a fuzzy process fuzzi ers infer ence engine defuzzi ers in a very e cient an exible manner...

The pseudoexhaustive testing (PET) scheme is a economic approach to test a large embedded programmable logic array (PLA). In this paper, we propose an efficient algorithm named low overhead PET (LOPET) to partition the product lines. By applying our algorithm, both the area overhead and test length are reduced significantly.

In the paper a method of logic synthesis of one-stage digital circuits on the base of Generic Array Logic (GAL) is proposed. Unlike the traditional approach to the logic synthesis on PLD, this method takes in account special internal resources and architectural features of GAL structures at the earliest stages of project design that allows increase the efficiency of logic synthesis. The conditi...

We have developed a fast programmable trigger processor board based on a field programmable gate array and a complex programmable logic device for use in the BELLE experiment. The trigger board accommodates 144 ECL input signals, 2 NIM input signals, 24 ECL output signals, and the VME bus specification. An asynchronous trigger logic for counting isolated clusters is used. We have obtained trigg...

We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and time (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow relative timing to simplify AES realization Field-Program...

A formal methodology for automatic hardwaresoftware partitioning and co-scheduling the tasks of an application between Microprocessor and Programmable Logic Devices (PLDs) has become emerging research area of hardware software co-design. The main objective of this research is to get full advantage of hardware utilization and speedup the application execution. Hardware software partitioning and ...