We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.

We show how logical frameworks can provide a basis for logic program synthesis. With them, we may use first-order logic as a foundation to formalize and derive rules that constitute program development calculi. Derived rules may be in turn applied to synthesize logic programs using higher-order resolution during proof that programs meet their specifications. We illustrate this using Paulson’s I...

We report on the benchmarks, participants and results of the third reactive synthesis competition (SYNTCOMP 2016). The benchmark library of SYNTCOMP 2016 has been extended to benchmarks in the new LTL-based temporal logic synthesis format (TLSF), and 2 new sets of benchmarks for the existing AIGER-based format for safety specifications. The participants of SYNTCOMP 2016 can be separated accordi...

The spectral information of a Boolean function provides data regarding the correlation between the input variables and the output of the function. This paper introduces a spectral based methodology for com-binational logic synthesis using linear transforms. An analysis of the properties of the spectra obtained from these transforms is provided and a synthesis algorithm using spectral techniques...

Logic synthesis has two stages of optimization: technologyindependent and technology-dependent. This paper surveys state-of-the-art methods for estimation and optimization of delays of logic circuits at technology-independent stage. Although at this stage we cannot completely predict nal delays after technology mapping, there exist reasonably accurate estimation techniques. Final delays can be ...

Implicit reachable state computation can be applied to a wide range of sequential formal veriication and logic synthesis problems. Symbolic manipulation with BDDs is one of the most eecient techniques known for the reachability analysis. The technique was rst proposed by Coudert et al. in 1989, and was improved later by Touati et al. in 1990. The standard approach chooses the cut of a sequentia...

This paper compares the ratioed logic circuits and conventional CMOS design. This comparison performed on efficient CMOS circuit realizations and the ratioed logic circuits and it is resulted in to superiority of ratioed circuit over the conventional CMOS in some cases with respect to area, input capacitance. In this paper, 4-input NAND gate is designed using the conventional CMOS design and ps...

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for e...

This paper presents the results of an observational study of industrial logic designers at Lamb Technion. The purpose of this study was to determine the current methods of logic design used in industry. These observations can be used to evaluate recent academic proposals of methods for generating controllers for machines, as well as suggesting new methods. By observing the logic designers it wa...