Double-Gate (DG) MOSFET has emerged as one of the most promising devices for logic and memory circuit design in sub 10nm regime. In this paper, we investigate the gate-to-channel leakage, EDT, BTBT and sub-threshold leakage for DG MOSFET. Simulations are performed using 2D Poisson-Schrödinger simulator with tight-binding Green’s function approach. Then we analyze the effect of parameter variati...

Ultrathin (UTD) and Nanoscale (NSD) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46nm and 1.6nm respectively, were fabricated using a selective “gate recessed” process on the same silicon wafer. The electrical transport characterization at room temperature has shown a large difference between the two kinds of devices and has been interpreted in terms of a huge unexp...

1) Introduction Recent systems are built of MOSFET transistors. Here, MO stands for metal oxide and FE for field effect. This means, that – in contrast to bipolar transistors – the gate is isolated by a metal oxide (today SiO2) and the channel is just controlled by the field through this oxide. Thus theoretically, the principal of MOSFET devices is that there is no current flowing through the g...

We present a novel n-type InGaAs quantum-well metal–oxide–semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III–V MOSFETs. The device structure features a composite InP/ Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have ...

A low-power CMOS voltage reference was developed using a 0.35 m standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolate...

Performance of n-type implant free In0.25Ga0.75As MOSFETs with Ga2O3 dielectric is investigated using ensemble Monte Carlo device simulations. The implant free MOSFET concept takes an advantage of the high mobility in III-V materials to allow operation at very high speed and low power. A 100 nm gate length implant free In0.25Ga0.75As MOSFET with a layer structure derived from heterojunction tra...

Rev. Abstract The most recent version (C2MTM) of Silicon Carbide (SiC) devices is used in a Zero Voltage Switching (ZVS) converter application. A 1200V, 160mohm SiC MOSFET from Cree Inc. is used to design a high-frequency ZVS LLC resonant fullbridge (FB) DC/DC converter. With the outstanding advantages of SiC MOSFET, which has lower junction capacitance and low-on-state resistor compared to a s...

One of effort to overcome the planar MOSFET’s limit is super-junction technology in high voltage power MOSFET. This technology can dramatically reduce both on-resistance and gate charge, which is usually a trade-off. With smaller parasitic capacitances, the super-junction MOSFETs have extremely fast switching characteristics and therefore reduced switching losses. Naturally fast switching behav...

The Screen-Grid Field Effect Transistor (SGrFET) is a planar MOSFET-type device with a gating configuration consisting of metal cylindrical fingers inside the channel perpendicular to the current flow. The SGrFET operates in a MESFET mode using oxide insulated gates. The multi-gate configuration offers advantages for both analog and digital applications, whilst the gate cylinder holes can be ex...

0038-1101/$ see front matter 2011 Elsevier Ltd. A doi:10.1016/j.sse.2011.06.022 ⇑ Corresponding author. Tel.: +1 510 664 4202; fax E-mail address: [email protected] (C. Shin A simple approach for manufacturing quasi-planar bulk MOSFET structures is demonstrated and shown to be effective not only for improving device performance but also for reducing variation in 6T-SRAM read and write ma...