In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, cov...

The earlier the stage where we perform low power design, the higher the dynamic power reduction we achieve. In this paper, we focus on reducing switching activity in high-level synthesis, especially, in the problem of functional module binding, bus binding or register binding. We propose an effective low power bus binding algorithm based on the table decomposition method, to reduce switching ac...

This paper proposes a two-level control strategy for wet clutches. On the low level, the control signal is calculated by solving a constrained optimal control problem. On the high level, the measured responses are used to update the system models and constraints that are used in the optimization for the next control signal. In this way a learning algorithm is obtained, which is able to optimize...

This paper deals with power minimization problem for datadominated applications based on a novel concept called partially guarded computation. We divide a functional unit into two parts – MSP (Most Significant Part) and LSP (Least Significant Part) and allow the functional unit to perform only the LSP computation if the range of output data can be covered by LSP. We dynamically disable MSP comp...