The newly proposed reconfigurable multiplier blocks offer significant savings in area over the traditional multiplier blocks for time-multiplexed digital filters or any other system where only a subset of the coefficients that can be produced by the multiplier block is needed in a given time. The basic structure comprises a multiplexer connected to at least one input of an adderhbtractor that c...

Multiplication is one of the basic functions used in digital signal processing (DSP). It requires more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all instructions in a typical processing unit is multiplier. The multiplier is a fairly large block of a computing system. The amount of circuitry involved is directly proportional to square of its resoluti...

ABSTRACT This paper introduces a digit-serial GF(2m) multiplier for use in the polynomial basis. The multiplier works with the most significant digit first and is scalable to an arbitrary digit size and can be constructed for any GF(2m). It is derived from a commonly used MSB first bit-serial multiplier, known as the standard shift-register multiplier. As the latency of the multiplier decreases...

The Multiplier Hopf Group Coalgebra was introduced by Hegazi in 2002 [7] as a generalization of Hope group caolgebra, introduced by Turaev in 2000 [5], in the non-unital case. We prove that the concepts introduced by A.Van Daele in constructing multiplier Hopf algebra [3] can be adapted to serve again in our construction. A multiplier Hopf group coalgebra is a family of algebras A = {A α } α∈π ...

In this paper, we present flexible multiprecision multiplier that combined variable precision, parallel processing (PP), razor based dynamic voltage scaling (DVS), and dedicated MP operand scheduling to provide optimum performance for variety of operating conditions. All of the building blocks of proposed flexible multiplier can either work as independent small precision multiplier or parallel ...

In this paper, we propose an MSD (most significant digit) multiplier based on an MSB (most significant bit) multiplier over GF(2). The proposed multiplier is based on connecting D (digit size)-bit bit-operations in series. In each digit operation in our proposed multiplier, the “left shift and reduction operation” is serially performed for each of D bits. Because registers for storing intermedi...

in this paper we introduce continuous $g$-bessel multipliers in hilbert spaces and investigate some of their properties. we provide some conditions under which a continuous $g$-bessel multiplier is a compact operator. also, we show the continuous dependency of continuous $g$-bessel multipliers on their parameters.

Experimental determination of solubility and ternary phase diagram of chiral compound are of tedious and time consuming tasks, and in many cases, there is not enough experimental data for different enantiomeric compositions to access the experimental ternary phase diagram. Using thermodynamic models with predictive capability, having less dependency on experimental data, affords a great advanta...

In this paper, a low-complexity Programmable Cellular Automata (PCA) based versatile modular multiplier in GF(2) is presented. The proposed versatile multiplier increases flexibility in using the same multiplier in different security environments, and it reduces the user's cost. Moreover, the multiplier can be easily extended to high order of m for more security, and low-cost serial implementat...

A low latency digit serial multiplier for GF(2m) that can be pipelined to the bit-level is presented in this paper. Unlike existing structures, the new multiplier does not put any restriction on the type of generator polynomial used or the digit size. Furthermore, the latency of the new multiplier is significantly less than the latency of the existing bit-level pipelined digit-serial multiplier...