A hardware implementation model is proposed that can be used in the design of stream ciphers, block ciphers and cryptographic hash functions. The cryptographic nite state machine (CFSM) model is no mathematical tool, but a set of criteria that have to be met by a real hardware nite state machine that will be used in the implementation of a cryptographic algorithm. Diiusion is studied by means o...

The physical layers of most wireless protocols are traditionally implemented in ASICs due to the heavy computation requirements. These solutions are costly to design and hardwired solutions that offer no post-programmability. In this paper, we introduce a flexible coprocessor architecture customized for wireless protocols. To accomplish the design, a complete baseband physical layer for the 802...

Deep and shallow convection calculations occupy significant times in atmosphere models. These calculations also present significant load imbalances due to varying cloud covers over different regions of the grid. In this work, we accelerate these calculations on Intel R © Xeon PhiTM Coprocessor Systems. By employing dynamic scheduling in OpenMP, we demonstrate large reductions in load imbalance ...

Smart card technologies have had a huge impact on the development of cryptographic techniques for commercial applications. The first cryptographic smart card was introduced in 1979. It implemented the Telepass 1 one-way function using 200 bytes! Next came smart cards with secret-key and public-key capabilities, respectively in 1985 and 1988. Implementing an RSA computation on a smart card was (...

In this paper we describe a high performance, area-efficient implementation of Hyperelliptic Curve Cryptosystems over GF(2). A compact Arithmetic Logic Unit (ALU) is proposed to perform multiplication and inversion. With this ALU, we show that divisor multiplication using affine coordinates can be efficiently supported. Besides, the required throughput of memory or Register File (RF) is reduced...

The NIST competition for developing the new cryptographic hash standard SHA-3 is currently in the third round. One of the five remaining candidates, Grøstl, is inspired by the Advanced Encryption Standard. This unique feature can be exploited in a large variety of practical applications. In order to have a better picture of the Grøstl-AES computational efficiency (high-level scheduling, interna...

Scheduling time impact on system performance increases especially when using dynamic priority algorithms, because of the enlarged computational effort at runtime. This overhead can be reduced by using dedicated hardware that does the time consuming computations necessary for scheduling. This can be a coprocessor capable of implementing dynamic scheduling algorithms which are, until now, rarely ...

Eclipse defines a heterogeneous multiprocessor architecture for high-performance streaming media as a subsystem of a system-on-silicon platform for the consumer electronics market. The scalable architecture template supports multiple function-specific coprocessors that operate in parallel and independently. Each coprocessor is multi-tasking, allowing multiple applications to proceed concurrentl...

This paper describes a new recon gurable processor architecture called REMARC (Recon gurable Multimedia Array Coprocessor). REMARC is a recon gurable coprocessor that is tightly coupled to a main RISC processor and consists of a global control unit and 64 programmable logic blocks called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decomp...

In this paper, we address the problem of improving the performance of real-time embedded Multiprocessor System-on-Chip (MPSoC). Such MPSoCs often execute applications composed of multiple tasks. The tasks on each processor are scheduled by a Real-Time Operating System (RTOS) instance. To improve performance, we reduce the Worst Case Execution Time (WCET) of the RTOS by new processor-coprocessor...