This paper enumerates low power, high speed design of TSPC (True Single Phase Clocking) D flip-flop having less number of transistors. This technique allows circuit to achieve lowest power consumption with minimum transistor count. Design of low power device is now an essential field of research due to increase in demand of portable devices. In the circuit as the scaling increase the leakage po...

Flip-flops and latches are the most important elements of a design for both a delay and energy point of view. In many electronics design low power consumption is basic need in most of the applications. The energy performance requirements enhance the most designers of next generation system towards the least possible power consumption. The power consumption is basically reduced by scaling of a p...

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous ...

This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops. Based on the simulation result...

Radiation effects account for increasing soft error occurrences in deep submicron circuits. A method for calculating an upper bound for the width of an erroneous pulse that may reach a flip flop or a primary output is presented. This is required in order to determine pulse removal (PR) circuit characteristics for error correction at each flip flop or primary output side. Key-Words: Soft errors,...

In this paper we propose, experimentally realize and study possible applications of a new type of logic element: random flip-flop. By definition it operates similarly to a conventional flipflop except that it functions with probability of 1/2 otherwise it does nothing. We demonstrate one practical realization of the random flip-flop based on optical quantum random number generator and discuss p...

flip-flop circuit technique has been designed. CMOS new flip-flop circuit with CMOS domino logic which, All the flip-flops were designed using UMC 180. Recognize standard circuit symbols for D Type flip-flops. though can be largely prevented by using the Edge Triggered D Type flipflop illustrated in Fig 5.3.3. locked loop, using 32 nm CMOS technology. Here we design D flipflop for Phase locked ...

We consider type IIB string theory compactified on an 8-dimensional Spin(7) manifold with N D5-branes, undergoing a conifold transition to a geometry with no branes and N units of dual 3-form RR flux through appropriate 3-cycles. We show that at constant IIB coupling, in the limit of large N and finite ’t Hooft coupling, this conifold transition can be lifted to a purely geometric S flop in the...

A low power pulse triggered flip-flop with signal feed through scheme using Conditional Pulse Enhancement technique is presented in this paper. The proposed design adopts a modified True Single Phase Clock Latch structure and employs a signal feed through scheme to enhance the delay. The long discharging path problem in conventional explicit type pulse triggered flip flops are successfully solv...

The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance CMOS circuits. Understanding the suitability of flipflops and selecting the best topology for a given application is an important issueto fulfill the need of the design to satisfy low power and high performance circuit. This paper presents a wides...