the present paper is an attempt to: 1- demonstrate how money is created (by the nature of the system), and to estimate the inflation resulting from monetary factors in both usurious and non-usurious systems. operational aspects of islamic and non-islamic banking systems are compared. 2- introduce a corrective term to be added to the multiplier of the supply of money, in order to prevent the und...

in this paper, we introduce the notion of multiplier in -algebra and study relationships between multipliers and some special mappings, likeness closure operators, homomorphisms and ( -derivations in -algebras. we introduce the concept of idempotent multipliers in bl-algebra and weak congruence and obtain an interconnection between idempotent multipliers and weak congruences. also, we introduce...

An improved oped for generating +40 voltage multiplier technique has been develV internally in p-channel MNOS integrated circuits to enrtble them to be operated from standard +5and : 12-V supply rails. With this technique, the multiplication efficiency and current driving capabtilty are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have ...

Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)-based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technolog...

We consider the Bresse beam with thermodiffusion effects act on bending moment and axial force together. An exponential stability is obtained in case of equal speeds propagation. Otherwise, a polynomial proved. Using frequency domain method together some multiplier techniques, we prove these results.

The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then shows the architecture for a 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra. The paper then extends multiplication to 16×16 Vedic multiplier using "Nikhilam Sutra" technique. The 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra uses four 8×8 Ved...

This paper proposes a 32 GHz band radar receiver with an X8 multiplier. The Ka-band Rx chip used in the was fabricated by using 28-nm complimentary metal-oxide-semiconductor (CMOS) process and its built-in multiplier enables to driven low reference signal of 4 GHz. designed attached ground plane microstrip patch antenna connected feedline via bonding wire. impedance matching circuit implemented...

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. The array multiplier and Braun array multipliers perform multiplication operation on unsigned numbers only. Thus, the requisite of the modern ...

The paper presents FPGA implementation of a spectral sharpening process suitable for speech enhancement and noise reduction algorithms for digital hearing aids. Booth and Booth Wallace multiplier is used for implementing digital signal processing algorithms in hearing aids. VHDL simulation results confirm that Booth Wallace multiplier is hardware efficient and performs faster than Booth’s multi...

Abstract—In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm t...