This paper presents a hierarchical genetic algorithm (GA) to solve the cell formation and layout decisions of cellular manufacturing. The intrinsic features of our proposed GA include using a hierarchical chromosome structure to encode concurrent cell design and layout decisions, developing a new selection scheme to dynamically considering two highly correlated fitness functions, and proposing ...

The multipliers are the key structure for designing high performance digital systems. Design considerations of multiplier include high speed, less power consumption, less PDP (power-delay product) and regularity of layout. These design parameters make it suitable for various compact low power VLSI implementations. This paper presents an application of the proposed XNOR-XOR cell for a 2x2 array ...

When an over-the-cell routing layer is available for standard cell layout, efficient utilization of that routing space over the cells can significantly reduce layout area. In this paper, we present three physical models to utilize the area over the cells for routing in standard cell designs. We also present efficient algorithms to choose and to route a planar subset of nets over the cells so th...

Cellular manufacturing (CM) is one of the most important subfields in the design of manufacturing systems and as a recently emerged field of study and practice, virtual cellular manufacturing (VCM) inherits the importance from CM. One type of VCM problems is VCM with alternative processing routes from which the route for processing each part should be selected. In this research, a bi-objective ...

In this paper, systematic mismatch due to parameter gradients is modeled and analyzed. A new layout strategy with flexible cell placement is proposed. Theoretical analysis shows its property of canceling the mismatch between two devices due to up to n order gradient effects by using 2 unit cells for each device. Simulation results show that the proposed technique gives better matching character...

This paper studies the device variability influence on 6T-SRAM cells in a function of the regularity level of their layout. Systematic and random variations have been analyzed when these memory circuits are implemented on a 45 nm technology node. The NBTI aging relevance on these cells has been also studied for two layout topologies and SNM has been seen as the parameter that suffers the highes...

A set of CAD tools for the synthesis and layout generation of multiple-valued current-mode CMOS logic (CMCL) circuits is described. The synthesis method is based upon the cost-table method. The general circuit structure, the cost-table functions and the decomposition procedure used in the cost-table synthesis program are explained. The synthesis program is based upon a logically complete set of...