The concept of an effective orthogonal cutting edge in turning is considered. The orientation of this edge in the radial-longitudinal plane, as commonly modeled through an effective lead angle, is studied. The methods of effective lead angle prediction used in numerous previously developed force models are plagued with large errors over ranges of process inputs, in particular feed rate and dept...

We present theoretical calculations of the Casimir force for Au thin films near the insulator-conductor transition that has been observed experimentally. The dielectric function of the Au thin films is described by the Drude-Smith model. The parameters needed to model the dielectric function such as the relaxation time, plasma frequency and the backscattering constant depend on the thickness of...

Optical Wireless Networks on-Chip have been recently proposed as alternative paradigm to overcome the communication bottleneck in computing architectures based on electrical networks. In this paper, we propose design of a 3×3 switching matrix for optical wireless on-chip interconnection. The exploits integrated phased arrays guarantee among three transmitters and receivers. work, effect multipa...

The use of a genetic algorithm for the minimum thickness design of composite laminated plates is explored. A previously developed genetic algorithm for laminate design is thoroughly revised and improved, by incorporating knowledge of the physics of the problem iota the genetic algorithm. Constraints are accounted for by combining fixed and progressive penalty functions. Improved selection, muta...

DS-CDMA with minimum mean square error frequency-domain equalization (MMSE-FDE) can provide much better performance than that with rake combining in a frequency-selective fading channel and is comparable to that of MC-CDMA with MMSEFDE. Chip interleaving is a form of channel interleaving that improves the DS-CDMA performance by converting the channel into a highly time-selective channel; the ti...

To build a system-on-chip (SoC) a common interface standard is necessary to connect ready-to-use components (IPs) from different vendors. Today several SoC interconnect standards, such as AMBA, Wishbone, OPB, and Avalon, are in use. We show in this paper that those standards have a common drawback for on-chip interconnections: They are built on the model of a common backplane bus that does not ...

Electrical discharge machining process is one of the most Applicable methods in Non-traditional machining for Machining chip in Conduct electricity Piece that reaching to the Pieces that have good quality and high rate of machining chip is very important. Due to the rapid and widespread use of alloy DIN1.2080 in different industry such as Molding, lathe tools, reamer, broaching, cutting guillot...

The sharply increased complexity of multi-core systems has motivated the architecture of Networks-on-Chip (NoC) to evolve from 2D to 3D. With the objective of optimizing 3D NoC system for specific applications, a new mapping scheme with the goal of reducing signal TSVs and peak temperature is proposed in this paper. The interlayer communication is optimized, which facilitates reduction of signa...

In this work we have proposed a geometric model that is employed to devise a scheme for identifying the hotspots and zones in a chip. These spots or zone need to be guarded thermally to ensure performance and reliability of the chip. The model namely continuous unit sphere model has been presented taking into account that the 3D region of the chip is uniform, thereby reflecting on the possible ...

Extensive work has been done on linear chip equalization of CDMA signals. In this paper we show how to apply the optimal chip equalization, which is shown to be part of the symbol Bayesian minimum mean square error estimator, and it is applicable for the downlink of a CDMA system with equal user powers. Although the optimal chip equalizer’s complexity is high, we believe it is worthy to study a...