Modular multiplication is fundamental to several public-key cryptography systems such as the RSA encryption system. It is also the most dominant part of the computation performed in such systems. The operation is time consuming for large operands. This paper examines the characteristics of yet another architecture to implement modular multiplication. An experimental modular multiplier prototype...

The salient feature of the composition operators for Gamma programs is that for termination, the parallel composition operator demands that its operands must terminate synchronously. This paper studies the inequational partial correctness properties of the combination of sequential and parallel composition operators for Gamma programs, provable from a particular compositional semantics (Brookes...

Absfmct-After a short introduction to on-line computing, we prove that the functions computable in on-line by a finite automaton are piecewise afthe functions whose coefikients are rational numbers (i.e., the fnnctions f(s) = UP + b, or f(z-, y) = nx + by + c where a. b, and c are rational). A consequence of this study is that multiplication, division, and elementary functions of operands of ar...

In this paper a divider-multiplier reusable library cell is presented. The division is implemented by means of a successive multiplication algorithm. The resulting structure uses a fixed-point format and two’s complement arithmetic for any size operands. It is coded with the VHDL synthetizable subset for the Synopsys Behavioral Compiler. The area and time delay results for different operand siz...

This paper presents a synthesisable VHDL model for a generalised multiplier capable of performing multiplication of both sign-magnitude and two’s complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand word-lengths thereby reducing automatic test generation, simulation and testing times. The model has been used successfully for generating m...

Residue number system (RNS) is a mathematical method to execute computing processes. In this method, the large operands which need more time to be calculated, convert to small ones to consume less time. In RNS, to decrease the delay time, some transistors used as a matrix to select output of operations in a transistor delay time. n this paper, by using of one-hot system in RNS, the used hardwar...

This paper presents a low-cost approach to concurrent error correction in high-performance CORDIC processors by using time-shared triple modular redundancy. Operands are partitioned into three sets of disjoint digits and operations are performed three times on different hardware components to correct possible errors by majority voting. The approach has limited latency increase and throughput re...

This paper describes FPgen, a test-program generator for datapath verification of floating-point units in microprocessors. FPgen is a convenient and powerful platform for generating interesting data combinations for floating-point instruction operands. Its main purpose is to provide a means to fulfill floating-point test-plans which typically include a myriad of tasks that stem from both the ar...

Fixed-angle rotation operation of vectors is widely used in signal processing, graphics, and robotics. Various optimized coordinate rotation digital computer (CORDIC) designs have been proposed for uniform rotation of vectors through known and specified angles. Nevertheless, in the presence of faults, such hardware architectures are potentially vulnerable. In this thesis, we propose efficient e...