An analysis of the efficiency of power-gating for clock storage elements (CSE) is presented. Two CSE topologies: the TGMS (Transmission Gate Master Slave) and the WPMS (Write Port Master Slave) are examined along with their respective circuits with sleep transistors. In this work, we study the benefits of adding sleep transistors coupled with regular clock-gating during inactive mode. We examin...

Power dissipation has become an overriding concern for VLSI circuits and it may come to dominate the total chip power consumption as the technology feature size shrinks. The main aim of this paper is to minimize the leakage power by using a ultra low leakage techniques. In this work we are choosing the Benchmark circuit as full subtractor . This full subtractor are designed by using different t...

The Discrete MultiTone (DMT) modulation system is an attractive method for a high speed data transmission over a nonflat channel with possible colored noise. The IFFT is used in its transmitter in order to divide the available frequency spectrum into large independent narrow band sub-channels. A high speed and an efficient lattice architecture is proposed to implement the IFFT. This will speed ...

Oxide material can make transparent devices with transparent electrodes. We developed a transparent oscillator and rectifier circuits with oxide TFTs. The source/drain and gate electrodes were made by indium thin oxide (ITO), and active layer made by transparent material of IGZO (Indium Gallium Zinc Oxide) on a glass substrate. The RC oscillator was composed of bootstrapped inverters, and 813 k...

This paper is based on analysis of a common source - common gate low noise transconductance amplifier (CS-CG LNTA). Conventional noise analyses equations are modified by considering to the low output impedance of the sub-micron transistors and also, parasitic gate-source capacitance. The calculated equations are more accurate than calculated equations in other works. Also, analyses show that th...

In this paper a comparison of static and dynamic parameters of CMOS logic circuits operated in standard and sub-threshold regimes is presented. Analytic models of logic threshold voltage, logic delay and power consumption are derived for the sub-threshold operation regime. Certain analytic models analogies between these two regimes are shown. Threshold voltages of inverter, NAND and NOR logic c...

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, wit...

Low power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates appeared in the literature recently. But they were all designed mostly by intuition and cleverness of the designer. ...

The latest technological progress of achieving the ultrastrong-coupling regime in circuit quantum electrodynamics (QED) systems has greatly promoted the developments of quantum physics, where novel quantum optics phenomena and potential computational benefits have been predicted. Here, we propose a scheme to accelerate the nontrivial two-qubit phase gate in a circuit QED system, where supercond...