This research work is focused on nondestructive evaluation of a five storied concrete frame structure of which construction was halted seven years ago. Before further construction could be started again it was imperative to assess the existing condition. For this purpose, load tests and core tests were performed on four floors from basement to first floor. It took more than one year to finish t...

This paper presents improvement of a core-based chip’s test control architecture that uses Std IEEE 1149.1 TAP to access core level register Test Control Blocks (TCB). We show enhancements for the register TCB, to improve its test coverage, to enable IEEE 1149.1 compliant RUNBIST and to optimize chip level TCB access. In addition, Test Control Expansion (TCE) is presented. TCE automatically val...

The main objective of core-based IC design is improvement of design efficiency and time-to-market. In order to prevent test development from becoming the bottleneck in the entire development trajectory, reuse of pre-computed tests for the reusable pre-designed cores is mandatory. The core user is responsible for translating the test at core level into a test at chip level. A standardized test a...

The Bunkie test, a functional performance test consisting of 5 test positions (performed bilaterally), has been used to assess aspects of muscular function. Current performance measures are based on clinical recommendations. The purpose of this study was to report normative data for a healthy population. One hundred and twelve subjects (mean age 25.9 ± 4.5 years) were recruited from a universit...

This paper analyzes the test memory requirements for core-based systems-on-a-chips and identifies useless test data as one of the contributors to the total amount of test data. The useless test data comprises the padding bits necessary to compensate for the difference between the lengths of different chains in multiple scan chains designs. Although useless test data does not represent any relev...

Explanation of the cover: The cover shows an example of an access infrastructure for a part of the Philips High Tech Campus, Eindhoven. In this thesis, test-access planning for embedded-core based system chips is addressed. The buildings in the cover can be considered as various cores in a system chip, while the roads correspond to test-access mechanisms. PROEFSCHIRFT ter verkrijging van de gra...

In the race against Moores Law, integrated chips (ICs) with multiple dies stacked over one another and connected by ThroughSilicon Vias (TSVs), called 3D TSV-Stacked ICs (SICs) have attracted a fair amount of research [1]–[5]. Due to imperfections in IC manufacturing, each individual chip must be tested. Testing each IC, increases cost, which is highly related to the testing time spent on each ...

A multi-purpose digital test core utilizing programmable logic has been introduced [1,2] to implement many of the functions of traditional automated test equipment (ATE). While previous papers have described the theory, this paper quantifies the results and presents additional applications with improved methods operating up to 4.4Gpbs. The digital test core provides a substantial number of prog...