The design of systems-on-chip requires simulation of highly abstracted models, such as SystemC Transaction Level Models (TLM), in addition to traditional register transfer level models. Due to the growing complexity of products, analyzing and understanding the behavior of the corresponding SystemC platforms becomes itself a challenge. Huge code bases are generally written by multiple authors an...

In this paper we present a SoC system able to perform Small-Vocabulary Automatic Speech Recognition (SVASR) based on Hidden-Markov Model (HMM) recognition techniques. Through in-depth analysis of the data-flow within the SPHINX 3 software [1], we create an efficient single-chip architecture tailored to the specific computational needs of a the system. By creating a tokenpassing scheme to contro...

This paper presents an overview of current ongoing research and design efforts conducted by Intelligent Optical Systems, Inc. in the area of hardware-based color segmentation. We discuss the specifics of the design of a microchip that combines a hardwired hybrid neural network with on-chip color imaging. Several preliminary tests show high approximation ability of our scheme. The single-chip im...

Abstract For multiple piece bone fractures orthopaedic surgeons often prefer drilling. During drilling (cortical and cancellous) heat is generated. Heat accumulation above tolerance level of biomaterial causes permanent injury. This leads to delayed restoration period. can be avoided by controlling drill tool geometrical aspects in depth information substructure. Among various angles tool, heli...

The last two decades have seen tremendous effort on the development of high-level synthesis algorithms for efficient realization of the multiplication of a variable by a set of constants using only addition, subtraction, and shift operations. These algorithms generally target the minimization of the number of adders and subtractors, assuming that shifts are realized using only wires due to the ...

The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extract functional equivalent structures, i.e. templates, from a control data flow graph. By inspecting the graph the algorithm generates all the possible templates and the corresponding matches. Using unique serial numbers ...

Computational microscopy tools, in particular lensfree on-chip imaging, provide a large field-of-view along with a long depth-of-field, which makes it feasible to rapidly analyze large volumes of specimen using a compact and light-weight on-chip imaging architecture. To bring molecular specificity to this high-throughput platform, here we demonstrate the use of plasmon-resonant metallic nanopar...

Previously, the interleavers is generated randomly for users of Interleave Division Multiple Access (IDMA) systems. Therefore, transmitting the entire chip-level interleaver matrix or power interleaver generation is required, which either adds redundancy or increases delay. In this paper, we propose to use deterministic chip-level interleavers for multiple users of IDMA systems. These chip-leve...

Due to power constraints, computer architects will exploit TLP instead of ILP for future performance gains. Today, 4–8 state-of-the-art cores or 10s of smaller cores can fit on a single die. For the foreseeable future, the number of cores will likely double with each successive processor generation. Hence, CMPs with 100s of cores–so-called large-scale chip multiprocessors (LCMPs)–will become a ...