In this paper, a novel technique for multiplication is presented using Vedic multiplier. Vedic multiplier uses adders and hence making fast adder will increase the overall speed for multiplication. We have done comparative analysis for multiplication using different architectures of adder. For comparison we have taken Carry Select Adder (CSA), Square Root Carry Select Adder (SQRT-CSA). We have ...

In this paper we explore the test complexity of the adder function with respect to the robust path delay fault model. A lower bound of (n 2) for the cardi-nality of a complete test set for a combinational n-bit adder is proven. This result is valid for any adder design known until now. In addition we present a fast O(p n)-time adder that is fully robust path delay fault testable with a test set...

We consider the design of two well-known optimal timeadders: the “carry look-ahead” adder [6] and the “conditional sum”adder 1131.It is shown that 6 log,(n) 4 and 6 log2(n) + 2 test patterns suffice tocompletely test the n-bit carry look-ahead adder and the n-bit conditionalsum adder with respect to the single stuck-at fault model (for a given setof basic cells).

Carry free arithmetic using higher radix number system such as Redundant Binary Signed Digit can be used to meet the demand for computers operating at much higher speeds. The computation speed can also be increased by using the suitable design of adder and multiplier circuits. Fast RBSD adder cells suggested by Neelam Sharma in 2006 using universal logic are modified in the proposed design by r...

In this paper we have find great applicability in RNS implementation for the Diminished-one modulo 2n+1 Adder using Circular Carry Selection (CCS) circuit. This adder presents a modulo addition of different bit values for n = 8, 12, 16, 24, 32, 48, 64. We are using the Diminished-one criteria using Circular Carry Selection (CCS) technique for the proposed modulo adder. The circuit design of pro...

Design and simulation of conventional CMOS full adder using 45nm technology at specified node has been presented here. This research work shows comparison about post layout simulations of designed low power CMOS full adder. It also explains about performance analysis of optimized low power CMOS full adder at different loads. This design has achieved 63. 11nW active power consumption with propag...