Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption. However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate...

the most enigmatic problems with the nearly 200 salt domes pierced in the persian gulf and in the zagros mountain ranges (zmr) in southern iran, a unique morphology in the world, have been the matter of this study, which is based on a combination of field work, enhancement of satellite and aerial photographs etc. in the zmr, structural anomalies are frequently associated with similar facies dis...

Memory testing commonly faces two issues: the characterization of detailed and realistic fault models, and the definition of time-efficient test algorithms able to detect them. Among the different types of algorithms proposed for testing Static Random Access Memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. The continuous evolution of the memory technolog...

This paper presents a modified nine switch inverter with two inputs and two Z-source networks. This inverter has two DC inputs and two AC outputs. Input DC voltages can be boosted to the required level. Amplitude, frequency and phase of AC output voltages can be controlled, independently. The proposed converter can be used in applications with two unregulated DC sources, which require feeding ...

Since Field programmable gate arrays (FPGAs) are reprogrammable, faults in them can be easily toleruted once fault sites are located. Previous researches on diagnosis of FPGAs mainly deal with faulty logic block. In this paper we present a method for the testing and diagnosis of faults in the interconnect structures of FPGAs. A predefined set of tests that can locate all single faults and many ...

Classical single stuck-at faults are analyzed as surrogates for any non-classical fault that may have caused an observed failure. Although multiple stuck-at faults are used as an illustrative example of non-classical faults, proposed algorithms are applicable to any other type of fault. Our effect-cause analysis is less complex than existing methods. The diagnostic procedure adds or removes fau...

We address delay faults: faults that cause a software component to take more time for completing an action than a given deadline. Such faults are particularly of interest in realtime mission-critical control applications that use general-purpose computing platforms to compute setpoints. A violation of realtime constraints associated with setpoints can result in failure. Existing benign and Byza...

The problem of fault detection and isolation of parametric faults is considered in this paper. A fault detection problem based on parametric faults are associated with internal parameter variations in the dynamical system. A fault detection and isolation method for parametric faults is formulated in a standard setup and a synthesis method for the fault detector is given. Further, fault detectio...

A study of the source-to-gate bridging faults at the transistor level in a CMOS circuit is presented in this brief paper. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It has been shown that such faults manifest either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equ...

Earthquake faults occur in interacting networks having emergent space-time modes of behavior not displayed by isolated faults. Using simulations of the major faults in southern California, we find that the physics depends on the elastic interactions among the faults defined by network topology, as well as on the nonlinear physics of stress dissipation arising from friction on the faults. Our re...