This report presents a method for automatic synthesis of asynchronous digital systems from high-level data ow speciications. We present an extended data ow model that accurately reeects the behavior of the asynchronous components so that the data ow spec-iication can be directly mapped into a hardware realization. In addition, we develop a timing model for the basic asynchronous building blocks...

This paper presents a new method for modeling and solving high-level synthesis problem. In our approach, finite domain constraints and related constraints solving techniques offered by constrained logic programming are used. They make it possible to define basic constraints on operations and registers and provide a way to find optimal or sub-optimal solutions to the data-path synthesis problem....

Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequential circuits. To reduce the power consumption of clock tree, previous work has shown that clock control logic should be synthesized in the high-level synthesis stage. However, previous work may suffer from a large circuit area overhead on the clock control logic. In this paper, we present an I...

Modern Integrated Circuits’ reliability and performance mainly depends upon its temperature and power due to the continuous process scaling. The IC peak temperature depends upon the power density of the IC. Thus, a power-aware High-Level Synthesis technique concentrates on the overall power reduction and is not appropriate for temperature-aware IC design. The temperature-aware design technique ...

Increasing digital system complexity and integration density motivate automation of the integrated circuit design process. High-level synthesis is a promising method of increasing designer productivity. Continued process scaling and increasing integration density result in increased power consumption, power density, and temperature. High-level synthesis for integrated circuit (IC) power and the...

This paper presents a methodology to design optimized electronic digital systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-level synthesis tools to automatically improve design structural quality (area measure). A two-stage, multiobjective optimization algorithm is used to search for circuits with the desired functionality subjected a...

Instruction scheduling is an optimization phase aimed at balancing the performance-cost tradeoffs of the design of digital systems. In this paper, a formal framework is tailored in particular to find an optimal solution to the resource-constrained instruction scheduling problem in high-level synthesis. The scheduling problem is formulated as a discrete optimization problem and an efficient popu...

Currently, a lot of research in the field of intelligent tutoring systems is concerned with recognising student’s emotions and affects. The recognition is done by extracting features from information sources like speech, typing and mouse clicking behaviour or physiological sensors. In former work we proposed some low-level speech features for perceived task difficulty recognition in intelligent...