In this paper we investigate iterative logic synthesis processes. A well known academic logic synthesis tool ABC incorporates many synthesis algorithms and scripts which may be run iteratively to possibly improve the result. When iterating the synthesis process, the whole network is considered. We propose an alternative approach to iterative synthesis – only properly selected parts of the circu...

We consider the problem of synthesizing protocols in a distributed setting satisfying specifications phrased in the logic of linear time and knowledge. In general, synthesis in distributed settings is undecidable already for lineartime temporal logic specifications, but there exist special cases in which synthesis from linear-time temporal logic specifications is known to be decidable. On the b...

Two regular circuit structures based on the programmable logic array (PLA) are proposed. They provide alternatives to the widely used standard-cell structure and have better predictability and simpler design methodologies. A whirlpool PLA is a cyclic four-level structure, which has a compact layout. Doppio-ESPRESSO, a four-level logic minimization algorithm, is developed for the synthesis of Wh...

System structure and a 2GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic. Introduction Domino logic is e...

ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduc...

Synthesis of quaternary quantum circuits involves basic quaternary gates and logic operations in the quaternary quantum domain. In this paper, we propose new projection operations and quaternary logic gates for synthesizing quaternary logic functions. We also demonstrate the realization of the proposed gates using basic quantum quaternary operations. We then employ our synthesis method to desig...

A circuit is reversible if it maps each input vector into a unique output vector, and vice versa. Reversible circuits lead to power-efficient CMOS implementations. Reversible logic synthesis may be applicable to optical and quantum computing. Minimizing garbage bits is the main challenge in reversible logic synthesis. This paper introduces an algorithm to generate the cascade of reversible comp...

We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An a...

In this paper we propose several methods of generating large benchmark circuits for testing logic synthesis tools. The benchmarks are derived from real circuits, so that they are functionally equivalent to their origins. We introduce misleading and/or redundant structures into them, making the benchmark size blow up significantly, with respect to the original circuit. Such benchmarks can be adv...