The Long Baseline Neutrino Oscillation Experiment (LBNE) is proposed to determine the neutrino mass hierarchy and measure the CP phase δCP in the leptonic sector. The current design of LBNE Phase I consists of a 10 kt liquid argon time projection chamber (LBNE10). The neutrino-antineutrino asymmetry in the electron-neutrino appearance probability has contributions from both the CP phase and the...

In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N, when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter·power Figure-Of-Merit (FOM). A subsampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP nois...

A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming...

An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional desi...

A 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial link without the reference clock is described. The CDR has a phase and frequency detector (PD and FD), which incorporates a half-rate bang-bang type oversampling PD and a half-rate frequency detector that can achieve low-jitter operation and improve pull-in range. The PD of oversamping method finds a phase error by generati...

This paper presents a CFAR detector based on the bootstrap for detecting signals with unknown amplitude, phase and frequency such as found in conventional pulsed radar and sonar systems. The detector is robust against non-Gaussian noise, and can still maintain the false alarm rate without much modification if consistent estimates are substituted for unknown parameters. Preliminary asymptotic re...

In this report we discuss the capabilities and limitations of the STAR detector to search for signatures of the QCD critical point in a low energy scan at RHIC. We find that a RHIC low energy scan will cover a broad region of interest in the nuclear matter phase diagram and that the STAR detector — a detector designed to measure the quantities that will be of interest in this search — will prov...

In this work, we derive the maximum a posteriori (MAP) symbol detector for a multiple-input multiple-output system in the presence of Wiener phase noise due to noisy local oscillators. As in single-antenna systems, the computation of the optimal receiver is an infinite dimensional problem and is thus unimplementable in practice. In this purview, we propose three suboptimal, low-complexity algor...

Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...