We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago. We then observe that those same design forces now are bearing down on the architects of contemporary general-purpose processors, who consequently are producing general-purpose processors whose architectural features are increasing...

This report introduces RAMP, an architectural model for long-term processor reliability measurement. With aggresive transistor scaling and increasing processor power and temperature, reliability due to wear-out mechanisms is expected to become a significant issue in microprocessor design. Reliability awareness at the microarchitectural design stage will soon be a neccessity and RAMP provides a ...

This paper presents an electronic second opinion system for the classification of mass abnormalities in mammograms into benign and malignant categories. This system is designed to help radiologists to reduce the number of benign breast cancer biopsies. Once a mass abnormality is detected and marked on a mammogram by a radiologist, two textural features, named denseness and architectural distort...

This thesis considers the definition and design of an embedded configurable DSP (Digital Signal Processor) core architecture and will address the necessary requirements for developing an optimizing high-level language compiler. The introduction provides an overview of typical DSP core architectural features, briefly discusses the currently available DSP cores and summarizes the architectural as...