In this paper, we explore the design issues of a shared bus with pipelinedprotocol, so called HiPi+Bus, which is implemented for a multiprocessor server. The characteristics and design parameters for the HiPi+Bus are described. In the viewpoint of a pipelined bus, a block transfer is no good because of involving complex and unbalanced pipeline. However, it is requested by a local cache memory o...

Waiting time in bus stops heavily affects traveler attitude towards public transportation and therefore is an important element for consideration when planning and operating a bus system. Furthermore, what passengers perceive as waiting time is often quite different from their actual waiting time at a bus stop. In this context, we present an empirical investigation of actual and perceived waiti...

-  Power system state estimation is a central component in energy management systems of power system. The goal of state estimation is to determine the system status and power flow of transmission lines. This paper presents an advanced state estimation algorithm based on weighted least square (WLS) criteria by introducing virtual meters. For each bus of network, except slack bus, a virtual meter...

An Improved Bus Signal Priority System for Networks with Nearside Bus Stops. (December 2004) Wonho Kim, B.S., Chungbuk National University; M.C.P., Seoul National University Co-Chairs of Advisory Committee: Dr. Laurence R. Rilett Dr. Amy Epps Martin Bus Signal Priority (BSP), which has been deployed in many cities around the world, is a traffic signal enhancement strategy that facilitates effic...

It has been a common practice in recent publications concerned with fault tolerance in VLSI and WSI to assume that interconnection buses can be designed to be almost defect-free by enlarging the width of the lines and the spacing between lines. Although this assumption may be valid in many cases, the cost-effectiveness of this proposed “robust” bus layout is questionable especially in the case ...

With little investment required for operating in streets, bus services are often designed to serve many overlapping routes with frequent stops. To upgrade services and attract choice riders, major bus routes should be provided with exclusive lanes, preferential signals, and fewer but more distinct stops. The Federal Transit Administration’s (FTA) Bus Rapid Transit (BRT) program is aimed at upgr...

This research is focused on the development of a model for estimating arterial travel time by utilizing Automatic Vehicle Location (AVL) system-equipped bus as a probe vehicle. As an initial achievement, a prototype arterial travel time estimation model, applied to the bus arrival time estimation, was developed. The methodology adopted in this phase of the travel time estimation model was the o...

The PCI Local Bus is used in all general purpose computer systems. Peripheral devices connected to this bus may perform transactions autonomously. If a processor accesses the main memory or performs an I/O instruction, the execution time of these operations depends on the working load of the PCI bus and of the communication protocols being used by the chip set. In this paper the influence of th...

Single bus. Shared-memory systems based on a single bus have some tens of processors, each one with a local cache, and typically suffer from bus saturation. A cache-coherence protocol in each cache snoops the traffic on the common bus and prevents inconsistencies in cache contents.’ Computers manufactured by Sequent and Encore use this kind of architecture. Because it provides a uniform access ...

ABSTRACT: A multiresolution AHB on-chip bus tracer named SYS-HMRBT (AHB multiresolution bus tracer) for versatile system-on-chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of needs. Experiments show that the bus tracer achieves very good compression r...