| Embedded systems present a tremendous opportunity to customize designs by exploiting the application behavior. Shrinking time-tomarket, coupled with short product lifetimes create a critical need for rapid exploration and evaluation of candidate System-on-Chip(SOC) architectures. Recent work on language driven Design Space Exploration (DSE) uses Architecture Description Languages (ADL) to cap...

The ever-increasing demands for bandwidth requirement, faster IP forwarding, efficient and effective firewall and flexible differentiated services has resulted in the evolution of sophisticated Network Processor Units (NPUs). We describe a novel approach to implement a pipelined, configurable IPv6 and IPv4 coprocessor for a Network Processor Unit. The coprocessor is capable of providing Forward...

This paper outlines research currently being conducted by the Cal Poly Intelligent Network Interface Card (CiNIC) project to develop a network coprocessor. The purpose of this coprocessor is to free the host machine from its network processing duties as well as to allow for additional functionality such as hardware-based firewalling or quality of service (QoS) support. We provide an overview of...

This paper presents a comparison of two possible approaches for the efficient implementation of a scalable Montgomery Modular Multiplication (MM) coprocessor on modern Field Programmable Logic Devices (FPLDs). The first implementation uses data path based on traditionally used redundant carry-save adders, the second one exploits standard carry-propagate adder with fast carry chain logic not yet...

HPRC (High-Performance Reconfigurable Computing) systems include multicore processors and reconfigurable devices acting as custom coprocessors. Due to economic constraints, the number of reconfigurable devices is usually smaller than the number of processor cores, thus preventing that a 1:1 mapping between cores and coprocessors could be achieved. This paper presents a solution to this problem,...

We present a novel technique which allows a virtual increase of the bitlength of a crypto-coprocessor in an efficient and elegant way. The proposed algorithms assume that the coprocessor is equipped with a special modular multiplication instruction. This instruction, called MultModDiv(A,B,N) computes A ∗ B mod N and (A ∗B)/N . In addition to the doubling algorithm, we also present two conceivab...

The Distributed Virtual Communication Machine (DVCM) is a software communication architecture for clusters of workstations equipped with programmable network interfaces (NIs) for high-speed networks. DVCM is an extensible architecture, which promotes the transfer of application modules to the NI. By executing ‘closer’ to the network, on the NI CoProcessor, these modules can communicate with sig...

Genetic information is increasing exponentially, doubling every 18 months. Analyzing this information within a reasonable amount of time requires parallel computing resources. While considerable research has addressed DNA analysis using GPUs, so far not much attention has been paid to the Intel Xeon Phi coprocessor. In this paper we present an algorithm for large-scale DNA analysis that exploit...

Polynomial multiplication is one of the most costly operations ideal lattice-based cryptosystems. In this work, we study its optimizations when operands has coefficients close to 0. We focus on structure since it at core Key Encapsulation Mechanisms submitted NIST call for post-quantum cryptography. particular, propose optimization operation embedded devices by using a RSA/ECC coprocessor that ...

A large range of applications exists with demand for high-performance point-to-point and point-tomultipoint communication. Existing communication subsystems frequently represent a major performance bottleneck. To overcome this bottleneck, a framework for high-performance multicast transfer protocol processing is presented, based on hardware support for multicast error control in transmitters an...