VLSI chips have been tested using various automatic test equipment (ATE). Although each ATE has a similar structure, the language for ATE is proprietary and it is not easy to convert a test program for use among different ATE vendors. To address this difficulty we propose a tester structure expression language, a tester language with a novel format. The developed language is called the general ...

The aim of built in self-test is to make the machine to test by itself. The best method among the built in self-test is pseudo exhaustive two pattern generation produces the output according to the input given with 16bit generator. The main drawback that occurs in this test pattern generation is maximum delay. It occurs in the carry generator module. In this paper, the method proposed with recu...

The paper aims to show that VLSI efficient implementations of Boolean functions (BFs) using threshold gates (TGs) are possible. First we detail depth-size tradeoffs for COMPARISON when implemented by TGs of variable fan-in (∆); a class of polynomially bounded TG circuits having O (lgn ⁄ lg∆) depth and O (n ⁄ ∆) size for any 3 ≤ ∆ ≤ clgn, improves on the previous known size O (n). We then procee...

Testing of VLSI chips is changing into significantly complicated day by day as a result of increasing exponential advancement of NANO technology. BIST may be a style technique that enables a system to check mechanically itself with slightly larger system size. During this paper, the simulation result performance achieved by BIST enabled UART design through VHDL programming is enough to compensa...

As the compactness of system-on-chip (SoC) increase, it becomes striking to integrate dedicated test logic on a chip. Starting with a broad idea of test problems, this survey paper focus on “Chip” Built in Self-Test (BIST) study and its promotion for board and system-level applications. This paper gives brief informative review of Built-in Self-test (BIST) and its testing techniques. Recently B...

Reliability and robustness have been always important parameters of integrated systems. However, with the emergence of nanotechnologies reliability concerns are arising with an alarming pace. The consequence is an increasing demand of techniques that improve yield as well as lifetime reliability of today’s complex integrated systems. It is requested though, that the solutions result in only min...

The two-dimensional discrete cosine transform (2D-DCT) is at the core of image encoding and compression applications. We present a new architecture for the 2D-DCT which is based on row-column decomposition. An efficient architecture to compute the one-dimensional fast direct (1D-DCT) and inverse cosine (1D-IDCT) transforms, which is based in reordering the butterflies after their computation, i...

Two asynchronous data communication mechanisms (ACMs) using self-timed circuits are presented. Mutual exclusion elements are used to concentrate potential metastability to discrete points so that it can be resolved entirely within the ACMs themselves. Self-timed circuits allow the minimisation of the interface between the reader and writer processes and the ACMs. Initial analysis shows that the...

This paper discusses size-optimal solutions for implementing arbitrary Boolean functions using threshold gates. After presenting the state-of-the-art, we start from the result of Horne and Hush [12], which shows that threshold gate circuits restricted to fan-in 2 can implement arbitrary Boolean functions, but require O(2/n) gates in 2n layers. This result will be generalized to arbitrary fan-in...