نتایج جستجو برای: field programmable gate array fpga implementation

تعداد نتایج: 1254713  

1998
Mohammad M. Mansour Ayman I. Kayssi

A novel hardware based design for the Internet Protocol version 6 (IPv6) router using Field Programmable Gate Array (FPGA) has been proposed. The router is implemented in Xilinx XCV1000BG560 FPGA, works at a clock frequency of 16 MHz with an average throughput of 980 Mbps.

2009
K. M. Deliparaschos S. G. Tzafestas

This paper focuses on the Field Programmable Gate Array (FPGA) design and implementation of intelligent control system applications on a chip, specifically fuzzy logic and genetic algorithm processing units. Initially, an overview of the FPGA technology is presented, followed by design methodologies, development tools and the use of hardware description languages (HDL). Two FPGA design examples...

1997
Jih-Jong Wang Brian E. Cronquist John E. McGowan Richard B. Katz

This paper describes the attributes and goals for a radiation-hard and high-reliability Field Programmable Gate Array (FPGA). The first Qualified Manufacturer List (QML) radiation-hardened antifuse FPGA, RH1280, is characterized. Its total dose and Single Event Effects (SEEs) are tested and the results are reported. Trade-offs and limitations in Single Event Upset (SEU) hardening are also discu...

2005
Ivan Kanev

The paper discuses the basic results from design and analysis of Field Programmable Gate Array (FPGA) based microcontroller for Voice Message (VM) system. The conditions that the system must answer, its architecture and instruction set are defined. The whole project, called VMCore, is implemented in VHDL and is tested on Altera ACEX 1K FPGA device.

2014
Pritamkumar N. Khose Vrushali G. Raut

An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilin...

A. Bilek H. Khati H. Talem R. Mellah

This paper presents an adaptive neuro-fuzzy controller ANFIS (Adaptive Neuro-Fuzzy Inference System) for a bilateral teleoperation system based on FPGA (Field Programmable Gate Array). The proposed controller combines the learning capabilities of neural networks with the inference capabilities of fuzzy logic, to adapt with dynamic variations in master and slave robots and to guarantee good prac...

2012
Andrej Trost Andrej Žemva

Programmable devices in the Field Programmable Gate Array (FPGA) technology enable design and prototyping implementation of complex digital systems executing their tasks on central processing units (CPU) and application-specific logic components. The paper presents development of a custom processor system in the FPGA device. The system is based on a CPU with an accumulator easily extendable wit...

2013
Stephen M. Killough Mohammed M. Olama Teja Kuruganti Stephen F. Smith

In recent years there has been great interest in using hybrid spread-spectrum (HSS) techniques for commercial applications, particularly in the Smart Grid, in addition to their inherent uses in military communications. This is because HSS can accommodate high data rates with high link integrity, even in the presence of significant multipath effects and interfering signals. A highly useful form ...

2003
Magnus Nilsson Chaminda Weerasinghe Serge Lichman Yu Shi Igor Kharitonenko

This paper presents a design and hardware implementation of a CMOS sensor based video camera incorporating a module, which combines the functions of automatic white balancing (A WB) and automatic exposure control (AEC). The finctionaliQ is achieved using dynamic control of sensor registers using I2C sensor interface. The image data processing is performed using a field programmable gate array (...

Journal: :JCSE 2017
Eui-Sub Kim Dong-Ah Lee Sejin Jung Junbeom Yoo Jong-Gyun Choi Jang-Soo Lee

NuDE 2.0 (Nuclear Development Environment 2.0) is a formal-method-based software development, verification and safety analysis environment for safety-critical digital I&Cs implemented with programmable logic controller (PLC) and field-programmable gate array (FPGA). It simultaneously develops PLC/FPGA software implementations from one requirement/design specification and also helps most of the ...

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