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Shared memory multiprocessors are widely used as platforms for technical and commercial computing [2]. Performance evaluation is a key technology for design in computer architecture. The continuous growth in complexity of systems is making this task increasingly complex [7]. In general, the problem of developing effective performance evaluation techniques can be stated as finding the best trade...

In this work we present the solution to the DEBS’2013 Grand Challenge, as crafted by the joint effort of teams from the Technion and TU Dortmund. The paper describes the architecture, details the queries and offers our observations regarding the appropriate way to trade-off high-level processing with time constraints.

A perennial problem in the process of developing signal processing systems is identifying an architecture which meets the computational and memory needs of the algorithm yet is still affordable in terms of cost, size, and complexity. To aid in making this decision, an architecture trade tool, using the Ptolemy kernel, has been developed. The purpose of this tool is to provide the user with an e...

Image compression demands high speed architectures for transformation and encoding process. Medical image compression demands lossless compression schemes and faster architectures. A trade-off between speed and area decides the complexity of image compression algorithms. In this work, a high speed DWT architecture and pipelined SPIHT architecture is designed, modeled and implemented on FPGA pla...

We describe a VLIW architecture designed speci cally as a target for dynamic compilation of an existing instruction set architecture. This design approach o ers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compil...

In this paper, we describe the architecture of the scheduling components integrated in a novel programmable processor architecture. The paper explores the requirements for scheduling in the environment of a network processor, designed for efficient protocol processing in high-speed networking. We focus on the implementation of services with weighted priorities and shaping of traffic on the tran...

For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has been presented to allow the development of the model for the specification, design and implementa...

This paper presents the Spread and Iterative Search (S&IS) motion estimation algorithm, which uses a random spread evaluation together with a central iterative evaluation to avoid local minima falls and to increase the image quality for high definition videos. Considering Full HD videos, S&IS reached an average PSNR gain of 1.41dB when compared to Diamond Search, with an increase of about four ...