The 2-Lagrange multiplier method is a domain decomposition method which can be used to parallelize the solution of linear problems arising from partial differential equations. In order to scale to large numbers of subdomains and processors, domain decomposition methods require a coarse grid correction to transport low frequency information more rapidly between subdomains that are far apart. We ...

This paper proposes the Field Programmable Gate Array (FPGA) architecture implementation of reconfigurable RootRaised Cosine (RRC), Finite Impulse Response (FIR) filter in which all the adders present in the designed filter are replaced by the modified Carry-Select Adders (CSLA), which is mostly used in Digital Up Converter (DUC). The proposed filter can be reconfigured with one of three differ...

In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency....

Processor speed largely governed by the multiplier architectures. It is desired to have faster ALU with lower power consumption for portable applications to have good battery life. Hence, there is need to address different multiplier architectures. In this paper, the analysis of 4-bit multiplier using a Vedic Mathematics (Urdhva Tiryagbhyam sutra) and conventional multiplier with two different ...

The Multiplier Hopf Group Coalgebra was introduced by Hegazi in 2002 [] as a generalization of Hope group caolgebra, introduced by Turaev in 2000 [], in the non-unital case. We prove that the concepts introduced by A.Van Daele in constructing multiplier Hopf algebra [3] can be adapted to serve again in our construction. A multiplier Hopf group coalgebra is a family of algebras A = {A α } α∈π , ...

This paper presents a high speed and low complexity modified radix-2 512-point Fast Fourier transform (FFT) architecture using an eight data-path pipelined approach for high rate wireless personal area network applications. A novel modified radix-2 FFT algorithm that reduces the hardware complexity is proposed. This method can reduce the number of complex multiplications and the size of the twi...

A 64 X64-bit iterating multiplier, the Stanford Pipelined Iterative Multiplier (SPIM), is presented. Tbe pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a Wallace tree for a VLSI implementation because it is a more regular structure. A 4:2 carry-save accumulator at the bottom of the array is used to iteratively accumulate partial products, allowing a p...

Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. For many signal processing, and graphics applications, it is acceptable to trade off some accuracy (in the least significant bit positions) for faster and better implementations. However, most of these modern applications need higher frequency or low latency of operations with minima...

Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing technology is an advanced transmission technique for wireless communication systems. In this paper, the 64 point pipeline FFT/IFFT processor is introduced for efficient implementation of OFDM architecture. The IFFT processor is used to modulate the subcarrier in transmitter section and FFT processor demodulate the subcarr...

In this paper, we propose a pipeline scheme for efficient realization of a complex multiplier using distributed arithmetic. The pipelined multiplier consists of one conventional multiplier that is multiplexed and some small additional circuitry on the boundary. The proposed scheme reduces the chip area as well as the interconnections by nearly half compared to a conventional complex multiplier....