-In this paper a low voltage Colpitts chaotic oscillator is proposed, based on an Electrically Programmable Analog Device matched Pair Mosfet Array (EPAD). The Oscillator is capable of producing chaotic carriers in very low supply voltages, this feature is very useful in mobile and low power consumption utilities. Key-Words: Chaos, Colpitts Oscillator, Low Voltage, EPAD.

We investigate the performances of 18 nm gate length AlInN/GaN, InP/InGaAs heterostructure and a Silicon double gate MOSFET, using 2D Sentaurus TCAD simulation. The heterostructure device uses lattice-matched wideband Al0.83In0.17N /InP and narrowband GaN / In0.53Ga0.47As layers, along with high-k Al2O3 as the gate dielectric, while silicon based device uses SiO2 gate dielectric. The device has...

BACKGROUND The ultrasonic transducer is one of the core components of ultrasound systems, and the transducer's sensitivity is significantly related the loss of electronic components such as the transmitter, receiver, and protection circuit. In an ultrasonic device, protection circuits are commonly used to isolate the electrical noise between an ultrasound transmitter and transducer and to minim...

Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the “nano-transistor” regime. This paper discusses performance characteristics of a MOSFET device with 15 nm physical gate length. In addition, aspects of a non-planar CMOS technology that bridges the gap between traditional CMOS and the nano-t...

Non-planar structures have been identified as promising structure for next device generation in the nanoelectronic era. However, the continuous device dimension scaling into nano regime eventually requires more sophisticated model due to the limitation of the existing models. A model for non-planar MOSFET structure was elaborated in this paper, especially for device with pillar structure, using...

As MOSFET dimensions are reduced to the sub-100 nm level, the electrical performance is critically dependent on the two-dimensional topology and concentrations of dopants in the semiconductor. In order to characterize, predict, and control the device topology, and hence the device behavior, it is essential to have a method of obtaining an accurate description of the 2-D profile. Moreover, knowl...

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates design of different analog digital using DGJLT. Amplifiers inverters are basic building block electronic ICs. A MOS amplifier converts variation to so...

The shrinking MOSFET has an increasing subthreshold leakage current caused by various mechanisms. For example, the band-to-band tunneling (BTBT) current from drain to channel results in a large subthreshold leakage current in a 50nm MOSFET [1]. Recently, the double-gate (DG) fully depleted (FD) MOS was investigated. In the DG-MOS, the channel region is intrinsic or lightly doped silicon so that...

-This paper presents a comprehensive on-line electrical characterization technique addressing the emerging Si/SiGe MOS technology. It demonstrates that the experimental high frequency and low frequency C V characteristics of Si/SiGe heterostructure MOS capacitors can provide accurate material-, process-, and device-related information such as: the valence band offset, Si cap layer thickness, su...

A comparison of full quantum device simulation with semi-classical methods is made for an unintended single atomistic dopant at various locations in a 10 nm double gate MOSFET transistor. The density gradient method comes closest to the non-equilibrium Green function results for fails seriously when the unwanted charge is located well-within the channel.