Today telecom network are growing complex. Although the amount of network performance data increased dramatically, telecom network operators require better performance on network performance data collection and analysis. Database is the important component in modern network management model. Since main memory database (MMDB) store data in main physical memory and provide very high-speed access,...

The main objective of this work was an efficient methodology for constructing low-level database tools that are built around a single-level store implemented using memory mapping. The methodology allowed normal programming pointers to be stored directly onto secondary storage, and subsequently retrieved and manipulated by other programs without the need for relocation, pointer swizzling or read...

There are several classes of operations, including I/O and memory allocation, that are considered difficult to perform as part of a transaction. To allow such operations inside of transactions, previous hardware transactional memory systems have proposed additional mechanisms such as opennested transactions that use hardware management of software handlers. Open-nested transactions are not nece...

We revisit classical sieves for computing primes and analyze their performance in the external-memory model. Most prior sieves are analyzed in the RAM model, where the focus is on minimizing both the total number of operations and the size of the working set. The hope is that if the working set fits in RAM, then the sieve will have good I/O performance, though such an outcome is by no means gua...

Mobile devices are in a widespread use today. Restricted by the features of mobile devices, such as mobility, low communication bandwidth, small capacity of memory, limited power and inconvenient interaction, mobile services are required to recommend items adapting to the user need and location. Much existing research on recommendations ignores semantic information of user dynamic historical pr...

Fast non-volatile memories are exposing inefficiencies in traditional I/O stacks. Though there have been fragmented efforts to deal with the issues, there is a pressing need for a high-performance storage stack. Interestingly, 20 years ago, networks were faced with similar challenges, which led to the development of concepts and implementations of multiple high-performance network stacks. In th...

An 18Mb DRAM has been designed in a 3.34, 0.5-pm CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. The chip output configuration defaults to 1 Mb x 18 for optimization of wafer screen tests, while 3 .34 or 5.04 operation is selected by choosing one of two M2 configurations. Selection of 2Mb x 9 or 1 Mb x 18 operation with the various address options, in exten...

In this paper, the problem of automatically mapping large-grain data ow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are inserted into the speci cation to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are re ned according t...

We propose and evaluate a simplified technique for studying the architectural behavior of database workloads. This “microbenchmark” technique poses simple queries of the database to generate the same dominant I/O patterns exhibited in more complex, fully-scaled workloads. The potential benefits from this microbenchmark approach include smaller hardware requirements, less extensive workload para...