A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system speciication will produce a particular response to a sequence of simulation commands. Three-valued modeling, where the third state X indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete veriicati...

This paper presents a hybrid CMOS-CNFET voltage controlled oscillator (VCO) with low power dissipation and linear response over a wide control voltage range. The hybrid circuit is based on PTM 32nm low power CMOS devices and 32nm CNFET devices with different threshold voltages. The VCO frequency and power dissipation are investigated for CNFET parameters such as number of nano-tubes, gate oxide...

This paper describes a transistor sizing methodology for both analog and digital CMOS circuits. Various techniques are used for power optimization in CMOS VLSI circuits. Transistor sizing is one of the important techniques for the determination of circuit performance. The aim of the power optimization is to minimize the power and power-delay product or the energy consumption of the circuit. Thu...

An additional stage for a Low Voltage Lazzaro’s Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. Electrical measurements of a prototype in CMOS 0.5μm technology verify the operation of the WTA circuit with VDD = 1.5V. Simulations in PSpice and stability issues are presented as well.

This paper introduces a high-speed high resolution CMOS current comparator which is used in an algorithmic Analog-to-Digital Converter (ADC) and implemented with a 0.6 μm standard CMOS process. Circuit occupies 170 x 80μm2. Proposed circuit performs comparison over a precision of 10bit at a 100MHz clock within the 0-250 μA input current range. Power consumption is less than 500 μA.

Historically, high-performance logic circuit interchip design has focused on bipolar emitter-coupled logic (ECL) circuits and signals, but VLSl CMOS has attained performance levels at which problems unique to its characteristics must be addressed for design optimization. In this paper, CMOS interchip circuit models are applied to develop packaging and wiring constraints for synchronous communic...

This paper provides new approach for nonvolatile Memristor-based Content Addressable Memory MCAM cell using memristor with CMOS processing technology in order to get high speed read/write operations within high packing density and low power dissipation. The proposed cell uses only two memristors as a memory cell and CMOS controlling circuitry which uses latching to decrease time required for wr...

After many decades of stunning progress in the shrinking of complementary metal-oxide-semiconductor (CMOS) devices, the steadily increasing difficulty in handling physical limitations as well as the rapidly increasing production and investment costs for each new technology generation will stop CMOS scaling in the not-too-distant future. Among the most challenging problems for further performanc...

We numerically investigate the possibility of using Tunnel field-effect transistor (TFET) in a 32 kHz crystal oscillator circuit to reduce power consumption. A simulation using SPICE (Simulation Program with Integrated Circuit Emphasis) is carried out based on a conventional CMOS transistor model. It is shown that the power consumption of TFET is one-tenth that of conventional low-power CMOS.

This paper concerns the design, implementation and subsequent experimental validation of a low-voltage analog CMOS switch based on a gate-bootstrapped method. The main part of the proposed circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved samp...