Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the Wallace tree structure with pipelining. A fast carry select adder is used for the final two-operand adder. It is shown that the time delay for the entire multiplier is O(log(n)). The design is particularly carried out for a 32-bit multiplier with two sections of pipelining, to bala...

An effective technique for phase noise improvement in a fractional-N synthesizer is described. The method requires using in a 90" phase shift lock a non-linear continuous-time or sampled-data block before the loop filter. Behavioral simulations on a fractional-N synthesizer incorporating different non-linear blocks and a second-order single bit sigma delta modulator show that it is possible to ...

The Wireless Identification and Sensing Platform (WISP) can be used to demonstrate and evaluate new RFID applications. In this paper, we present practical results of an implementation of elliptic curve cryptography (ECC) running on the WISP. Our implementation is based on the smallest recommended NIST elliptic curve over prime fields. We meet the low-resource requirements of the platform by var...

In this paper we present an ultra low power all digital DLL operating near threshold voltage with lock in range of 80 200MHz. The DLL is immune to false locking problem and dithering around the lock point. Besides clock de-skewing and multiphase clock generation it can multiply the frequency by four. The DLL is implemented in 45nm PTM and operates at 0.7 V and dissipates 120uW at 200MHz. Keywor...

Rovibrational absorption spectra of methyl chloride in the spectral region between 2800 and 3200 cm were recorded with a high-resolution Fourier spectrometer. A multispectrum fitting procedure was used to analyze 527 transitions of the ν1 band and to retrieve the selfbroadening coefficients for various Jand K-values with an estimated accuracy around 8%. Pure rotational transitions of CH3Cl in t...

This paper proposes a variable-modulus injectionlocked frequency multiplier for better harmonic suppression. It is more suitable for fully-integrated implementation using low-Q on-chip inductors in digital CMOS than conventional approaches. A prototype dual-modulus frequency doubler/tripler with 1.6GHz input and 3.2GHz/4.8GHz output is implemented in a 0.18 m standard digital CMOS. At 5% lockin...

This paper presents the simulation results of a 4ˆ4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 —m standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition freque...

We present a new low-complexity bit-parallel canonical basis multiplier for the field GF(2 m ) generated by an all-onepolynomial. The proposed canonical basis multiplier requires m 2 1 XOR gates and m 2 AND gates. We also extend this canonical basis multiplier to obtain a new bit-parallel normal basis multiplier.

In the recent year growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. In this paper a low power bypassing -based multiplier design is present, in which reduction in power...