Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ productivity. In this paper, we present a practical method to perform gate sizing, taking also into account the contribution of fixed wiring loads. Closed-form bounds are derived and a simple recursive procedure is develope...

Analog circuits form an important part in integrated circuits and in particular in ASICs (Application Specific Integrated Circuits). However, due to the high complexity, design of this part has become a bottle-neck in the design flow (Gielen, 2007; Rutenbar et al., 2007). To overcome this problem and to guaranty that the analog part can be designed in reasonable time even for future technologie...

Restructuring the recent developments in the power system and problems arising from construction as well as the maintenance of large power plants lead to increase in using the Distributed Generation (DG) resources. DG units due to its specifications, technology and location network connectivity can improve system and load point reliability indices. In this paper, the allocation and sizing of di...

We derive a compiler for ML-style pattern matches. It is conceptually simple and produces reasonably good compiled matches. The derivation is inspired by the instrumentation and partial evaluation of na ve string match-ers. Following that paradigm, we rst present a general and na ve ML pattern matcher, instrument it to collect and exploit extra information, and show that partial evaluation of t...

We derive a compiler for ML style pattern matches It is conceptu ally simple and produces reasonably good compiled matches The derivation is inspired by the instrumentation and partial evaluation of na ve string match ers Following that paradigm we rst present a general and na ve ML pattern matcher instrument it to collect and exploit extra information and show that partial evaluation of the in...

Many methods have been developed for structural size and configuration optimization in which cross-sectional areas are usually assumed to be continuous. In most practical structural engineering design problems, however, the design variables are discrete. This paper proposes two efficient structural optimization methods based on the harmony search (HS) heuristic algorithm that treat both discret...

This paper considers the problem of interconnect wire delay in digital integrated circuits. The correct wire sizing and buffer insertion/sizing can reduce the interconnect delay. The interconnect wire is divided into segments and to optionally buffers are inserted between two adjacent segments. But it is important to select appropriate values for the size of buffers as well as the lengths and w...