نتایج جستجو برای: time verification

تعداد نتایج: 1949637  

Control of sedimentation in reservoirs of dams is considered to be one of the most important issues in exploitation of dams and increasing their useful life. Reservoirs act as traps for sediments and prevent transport of sediments to the river. The deposited sediments will decrease the capacity of the reservoirs so that they cannot be in use any more. Various methods are discussed in this study...

2011
Liah Kor Amos Korman David Peleg

This paper establishes tight bounds for the Minimum-weight Spanning Tree (MST) verification problem in the distributed setting. Specifically, we provide an MST verification algorithm that achieves simultaneously Õ(|E|) messages and Õ( √ n+D) time, where |E| is the number of edges in the given graph G and D is G’s diameter. On the negative side, we show that any MST verification algorithm must s...

2004
Jean-François Boland Claude Thibeault Zeljko Zilic

Verification is a major bottleneck in today’s design flow. As the functional verification is time consuming, it is constantly being reconsidered. We propose a new verification framework based on the SystemC verification standard that uses MATLAB and Simulink to accelerate testbench development. Our major contributions are first a cosimulation interface between SystemC and MATLAB and Simulink, a...

Journal: :Electr. Notes Theor. Comput. Sci. 2006
David J. Musliner Michael J. S. Pelican Robert P. Goldman

The CIRCA system automatically synthesizes hard real-time discrete event controllers from plant and environment descriptions. CIRCA’s automatically-synthesized controllers provide guaranteed real-time performance and safety preservation in adversarial, non-closed-world domains. By separating controller construction from formal controller verification, CIRCA makes controller synthesis decisions ...

2015
Disha Goswami Dharmesh J. Shah

Now day’s functional verification is a very hot topic. With the growing complexity of modern digital systems and embedded system designs, the task of verification has become the key to achieving faster time-to-market requirement for such designs. Verification is the most important aspects of the ASIC design flow. It is estimated that between 40 to 70 percent of total development effort is consu...

2001
Pao-Ann Hsiung Shu-Yu Cheng

Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often flatten out the behavior of a target system before verification. Inherent modularities, either explicit or implicit, functional or structural, are not exploited by these tools and algorithms. In this work, we show how as...

Seyed-Hosseini , S.M., Heydari, R. , Heydari, T. ,

Bus network design is an important problem in public transportation. The main step to this design, is determining the number of required terminals and their locations. This is an especial type of facility location problem, a large scale combinatorial optimization problem that requires a long time to be solved. Branch & bound and simulated annealing methods have already been used for solving Urb...

Journal: :Electr. Notes Theor. Comput. Sci. 2005
Anders Henriksson Uwe Aßmann James Hunt

We propose a new development scheme for quality-aware applications, quality-driven development (QDD), based on the Model-Driven Architecture (MDA) of OMG. We argue that software development in areas, such as real-time systems, should not only rely on code verification, but also on design verification, and show that a slightly extended MDA process offers the opportunity to integrate system devel...

2011
Finnian Kelly Naomi Harte

The changes that occur in the human voice due to ageing have been well documented. The impact of these changes on speaker verification is less clear. In this work, we examine the effect of long-term vocal ageing on a speaker verification system. On a cohort of 13 adult speakers, using a conventional GMM-UBM system, we carry out longitudinal testing of each speaker across a time span of 30-40 ye...

Journal: :Journal of Systems and Software 2017
Srinivas Pinisetty Thierry Jéron Stavros Tripakis Yliès Falcone Hervé Marchand Viorel Preoteasa

Runtime verification (RV) techniques are used to continuously check whether the (untrustworthy) output of a black-box system satisfies or violates a desired property. When we consider runtime verification of timed properties, physical time elapsing between actions influences the satisfiability of the property. This paper introduces predictive runtime verification of timed properties where the s...

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